Internal line connection method for field-programmable gate array

Abstract

The invention provides an internal line connection method for a field-programmable gate array. The method comprises the following steps of: dividing internal modules of the field-programmable gate array along edges of the internal modules; constructing, namely constructing transverse connection modules and longitudinal connection modules according to the types of the internal modules respectively; and connecting, namely connecting the internal modules in turn by using the transverse connection modules which are connected with the internal modules in a transverse direction and the longitudinal connection modules which are connected with the internal modules in a longitudinal direction, wherein the transverse connection modules and the longitudinal connection modules comprise at least one of internal connection lines of which the starting points are inside the internal modules, access connection lines which are connected with the inner part of the internal modules and the edges of the internal modules, and cross connection lines of which the start points are inside the edges of the internal modules respectively.

Description

technical field [0001] The invention relates to a method for interconnecting wires inside a field programmable gate array. Background technique [0002] FPGA (Field-Programmable Gate Array, that is, Field Programmable Gate Array) includes: LUT (Lookup Table, that is, lookup table), flip-flops and latches that implement user logic, and MUX (Multiplexer, multiplexer) that implements connection relationships selector) and interconnect lines. EDA (Electronic Design Automation, electronic design automation) tools need to model each module of the FPGA, among which modeling the top-level interconnection of the FPGA is the key point, the number of top-level interconnection lines: [0003] COUNT INTER =K INTER *TILE COUNTX *TILE COUNTY (Formula 1), [0004] where TILE COUNTX and TILE COUNTX Respectively represent the array size of the functional unit (internal module) of the FPGA, K INTER It is the number of interconnection lines associated with each functional unit...

AI Technical Summary

Problems solved by technology

There are two conventional interconnection models: one is to model each interconnection separately, which is not a good choice in terms of space or processing time; the other is to merge interconnections of the same type, but Due to the differences in interconnection logic and views, the processing of interconnection models becomes complicated, and it is difficult to improve the complexity of the above problems, and it is difficult to deal with large arrays of commercial FPGAs

Images