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Processor

A processor and buffer technology, applied in the fields of instruments, electrical digital data processing, machine execution devices, etc., can solve the problems of non-interchangeability, increase in code size, etc., to improve parallelism, reduce the decline of grouping efficiency, and improve performance Effect

Inactive Publication Date: 2012-04-18
SOCIONEXT INC
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, there are problems such as an increase in code size due to insertion of NOP instructions and non-compatibility with existing instruction sets.

Method used

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Experimental program
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Embodiment Construction

[0041] First, after describing a general processor having a superscalar architecture, the processor according to this embodiment will be described.

[0042] figure 1 It is a drawing comparing execution performance obtained by two types of instruction groups.

[0043] figure 1 The comparison diagram of is composed of columns of instruction code 101 , ideal result 102 and past result 103 .

[0044] In the instruction code 101, the instruction code constituting the loop processing is shown, and the instruction code 101 includes a label of a branch destination, a mnemonic representation of the instruction code, and a resource to be referred to or defined by the instruction.

[0045] Here, a processor (not shown) that executes each instruction indicated by the instruction code 101 can execute a maximum of three instructions in parallel, and each of them consists of a load-store operator, a product-sum operator, an arithmetic operator, and branch execution unit. However, the ess...

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PUM

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Abstract

A processor is provided with instruction buffers (401-403) which store a plurality of instructions to be issued to a plurality of computing units, dependence relationship detection u its (431, 432) which detect a first dependence relationship that is a dependence relationship existing between arbitrary defined two instructions stored in the instruction buffers and a second dependence relationship that is a dependence relationship existing between the respective instructions stored in the instruction buffers and respective instructions that are already issued, and determine a group of instructions that have neither the first dependence relationship nor the second dependence relationship among the plurality of instructions stored in the instruction buffers as a group of instructions capable of being issued to the plurality of computing units, and dispatch units (441-443); which issue the instructions included in the determined group to the plurality of computing units.

Description

technical field [0001] The invention relates to a processor capable of executing multiple instructions in parallel, in particular to a processor with a superscalar architecture. Background technique [0002] The processor executes the sequences of instructions stored in the memory. In order to improve execution performance, when executing an instruction sequence, it is best to make it execute multiple instructions that can be executed in parallel. [0003] Among processor architectures that can execute multiple instructions in parallel, there is something called superscalar. Using superscalar technology, when the definition of a certain resource (register, etc.) is not completed by the instruction that is already being executed, the issuance of the instruction that refers to the resource is stopped, and the use of the next non-dependent instruction is implemented first Hardware control. [0004] However, the above-mentioned superscalar technique requires a complicated mec...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F9/38
CPCG06F9/3814G06F9/3885G06F9/3838
Inventor 山名智寻
Owner SOCIONEXT INC