Dynamic random access memory (DRAM) and method for improving DRAM data access bandwidth

Abstract

The invention discloses a dynamic random access memory (DRAM) and a method for improving DRAM data access bandwidth. The method includes refreshing logic optimization, specifically includes the following steps: S11, obtaining a longest time interval which is required for completing refreshing of four web ready appliances protocols (WRAPs), dividing the longest time interval into a first stage and a second stage; S12, setting priority level of reading / writing logic to be higher than that of refreshing logic at the first stage, wherein the refreshing logic automatically selects Bank which is not used by the reading / writing logic to perform refreshing; and S13, setting the priority level of the reading / writing logic to be lower than that of the refreshing logic, wherein the refreshing logic refreshes the Bank which is not refreshed. Under the condition that the memory access clock frequency is not improved, the interface data bit width is not increased, and the logic design complexity is not increased, the DRAM and the method for improving the DRAM data access bandwidth improve interface data access bandwidth to the most extent, and meet requirements for data storage of integrated circuit (IC) design.

Description

technical field [0001] The invention relates to the field of integrated circuit design, in particular to a DRAM memory and a method for maximizing the data access bandwidth of the DRAM interface. Background technique [0002] At present, there are two main forms of storage of large amounts of data in IC (integrated circuit) design: external memory and embedded memory. Among them, the external memory needs to design more complex interface logic, and more IC external interface pin signals are added, which leads to an increase in the cost of the IC itself and the system. In addition, it is difficult for the external memory to achieve a higher access speed. Therefore, in the current IC design, the data memory is embedded in the IC as much as possible. There are also two options for embedded memory: SRAM (Static Random Access Memory) and DRAM (Dynamic Random Access Memory). Compared with SRAM, due to the different process, DRAM has great advantages in embedded design. It has si...

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Problems solved by technology

[0004] However, the above-mentioned prior art also has deficiencies. Increasing the width of the data interface will also increase the data width in other auxiliary logic of the interface, which will lead to more resources used in the entire logic design and an increase in the area of ​​the IC. This leads to an increase in the cost of the IC; increasing the interface clock frequency alone will cause the main clock frequency in the entire IC to be lower than the DRAM clock frequency, so that the data interface needs to be switched between the two clock domains, thereby increasing the interface Design Difficulty, Logic Resource Usage, and IC Area

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