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Method for reducing transient power consumption

A transient power consumption and clock technology, applied in special data processing applications, instruments, electrical digital data processing, etc., can solve problems such as damage, failure to work, and functional errors

Inactive Publication Date: 2012-05-30
SHANGHAI HUAHONG INTEGRATED CIRCUIT
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

When the transient power consumption of the integrated circuit chip exceeds its threshold, the function of this product may malfunction, fail to work or be directly destroyed

Method used

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  • Method for reducing transient power consumption
  • Method for reducing transient power consumption
  • Method for reducing transient power consumption

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Embodiment Construction

[0027] specific implementation plan

[0028] The technical solutions proposed by the present invention will be described in detail below in conjunction with the accompanying drawings.

[0029] Such as figure 1 As shown in , it is assumed that there are 3 clock domains in the circuit design, namely clk0, clk1 and clk2, and there is a fixed phase relationship between clk1 and clk2.

[0030] Assuming that the CP delay of clk1 is Dclk1, and the CP delay of clk2 is Dclk2, when the phase difference between Dclk1, Dclk2 and the two clock domains is 0, the registers in circuit combinations 1 and 2 with the same characteristics will be at time T1 At the same time, it is assumed that the power consumption required for the flipping of all registers in circuit combination 1 is P1, the power consumption required for flipping all registers in circuit combination 2 is P2, and the power consumption of all circuits except the registers of circuit combination 1 and 2 is Po1, then the total po...

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Abstract

The invention relates to a method for reducing transient power consumption. The flip rate of a circuit in a peak period is reduced via interference to a clock path, so as to reduce the transient power consumption of the circuit. The implementation steps comprise analyzing the characteristics of distribution of the transient power consumption in the circuit, and determining the clock path branches; adding or removing buffers on the clock path branches to ensure that the delays of the clock path branches are different to avoid the flipping time; and repairing the time sequence resulting from the clock path delays under the interference. By adopting the method, the transient power consumption in the circuit design can be reduced effectively, and normal operation of the circuit can be ensured.

Description

technical field [0001] The invention relates to a method for reducing power consumption in integrated circuit design, in particular to a method for reducing transient power consumption. Background technique [0002] Today's integrated circuit products have been widely used in people's daily life, such as bus IC cards, social security cards, and ID cards, which greatly facilitate people's basic necessities of life. No matter what kind of integrated circuit product, with the development of technology, the requirements for its working performance and production cost are getting higher and higher, such as operating frequency, power consumption, stability and integrated circuit chip size and so on. Among them, power consumption is a very important technical indicator of integrated circuit products, and power consumption is usually divided into average power consumption and transient power consumption. The average power consumption determines the energy consumption of the product...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F17/50
Inventor 王永流张伸
Owner SHANGHAI HUAHONG INTEGRATED CIRCUIT
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