6T CMOS (complementary metal oxide semiconductor) SRAM (static random access memory) unit

Abstract

The invention discloses a 6T CMOS (complementary metal oxide semiconductor) SRAM (static random access memory) unit which comprises two NMOS (negative-channel metal oxide semiconductor) transmission gate transistors, two PMOS (positive-channel metal oxide semiconductor) pull-up transistors and two NMOS pull-down transistors, and is characterized in that sources of the PMOS pull-up transistors are connected with word lines connected with gates of the NMOS transmission gate transistors, and the threshold voltage of the NMOS transmission gate transistors is higher than a voltage value on the word lines in a standby state. Potential during standby is significantly lower than the high potential during reading and writing and standby electric leakage is further reduced by connecting the sources of the pull-up transistors, which are originally connected to a high voltage, and the gate ends of the transmission gate transistors with the word lines.

Description

technical field [0001] The invention relates to the field of semiconductor integrated circuit design, in particular to a 6T CMOS SRAM unit. Background technique [0002] In VLSI (Very Large Scale Integrated Circuits) design, power consumption has become an increasingly important feature. Among all the power consumption, the standby leakage (stand-by leakage) consumption of SRAM (Static Random Access Memory, static random access memory) is a very significant part. refer to figure 1 , figure 1 It is the most commonly used basic 6T CMOS SRAM cell, including two NMOS pass-gate transistors 102, two PMOS pull-up transistors 104 and two NMOS pull-down transistors 106, the drains of the two PMOS pull-up transistors 104 are connected with the high voltage (Pdd), the sources of the two NMOS pull-down transistors 106 are connected with the low voltage, and the gate of the transmission gate transistor 102 is connected with the word line (wordline), for For this 6T SRAM unit, in orde...

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Problems solved by technology

refer to figure 1 , figure 1 It is the most commonly used basic 6T CMOS SRAM cell, including two NMOS pass-gate transistors 102, two PMOS pull-up transistors 104 and two NMOS pull-down transistors 106, the drains of the two PMOS pull-up transistors 104 are connected with the high voltage (Pdd), the sources of the two NMOS pull-down transistors 106 are connected with the low voltage, and the gate of the transmission gate transistor 102 is connected with the word line (wordline), for For this 6T SRAM unit, in order to reduce the standby leakage of SRAM, the most common method is to increase the threshold voltage of the SRAM unit device, but this method will not only delay the access of the storage unit, but also increase the internal node switching voltage of the storage unit mismatch, which also limits the minimum supply voltage

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