Single instruction multiple data (SIMD) vector processor supporting fast Fourier transform (FFT) acceleration

Abstract

The invention discloses a single instruction multiple data (SIMD) vector processor supporting fast Fourier transform (FFT) acceleration, which comprises a control unit, a calculation unit, a storage subsystem, a storage weaving unit and an address generation unit. The calculation unit supports quick processing of various vector calculations. The storage subsystem comprises three storage groups. Each storage group comprises four storage bodies, the bit wide of a single storage body in each storage group is a plural character, and the storage groups support plural vector calculation with concurrent four-way data and real number vector calculation with concurrent eight-way data. The calculation unit, the address generation unit and the storage weaving unit are connected with the control unit. The address generation unit generates required operand address sequence, coefficient address sequence and result address sequence. The storage weaving unit and the address generation unit are connected with the calculation unit to achieve address mapping of the storage bodies. The acceleration efficiency of the SIMD vector processor to FFT / inverse fast Fourier transform (IFFT) calculation corresponds to a special hardware accelerator. The SIMD vector processor avoids huge extra pay expenses brought by use of the special hardware accelerator, and is suitable for being used in a real-time signal processing system with a large amount of long vector calculation.

Description

Technical field [0001] The present invention relates to a SIMD vector processor that supports FFT acceleration and a design method thereof, in particular to a SIMD vector processor that supports variable number of points, has high FFT / IFFT operation acceleration efficiency and low overall hardware overhead. Its design method. Background technique [0002] Fast Fourier Transform (Fast Fourier Transformation, FFT) operations are generally completed by dedicated hardware accelerators (called FFT processors) or DSP processors. Dedicated hardware accelerators can achieve higher acceleration efficiency, but will take up more additional resources, including on-chip storage resources and on-chip computing logic resources, especially when the length of the transformation is extremely large, the additional resources occupied by the dedicated hardware accelerator will not be able to bear . Although the FFT operation is completed by way of DSP processor software programming, it does not ta...

AI Technical Summary

Problems solved by technology

SIMD vector processors can be used to accelerate regular vector operations, but there is no SIMD vector processor that can directly accelerate FFT operations at the same time (acceleration efficiency is comparable to that of dedicated accelerators). In this case, an additional FFT hardware accelerator is needed to accelerate For FFT / IFFT operations of various points, additional on-chip resources will be occupied

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