Method for solving communication deadlock of I2C (Inter-Integrated Circuit) bus

Abstract

The invention discloses a method for solving the communication deadlock of an I2C (Inter-Integrated Circuit) bus. The I2C bus comprises a serial data line (SDA) and a serial clock line (SCL); the I2C bus is provided with a host and at least one slave; the method for solving the communication deadlock of the I2C bus comprises a host-based implementation method, wherein the implementation method comprises the following steps of: (A) monitoring a working state of the I2C bus, wherein the I2C bus is in a deadlock state if the host cannot send detection information to the slave of the I2C bus; (B) when the I2C bus is in the deadlock state, resetting a host module, and controlling the SCL to generate a clock pulse signal so as to unlock the slave of the I2C in the deadlock state; and (C) after unlocking the slave, reinitializing the host module to enable the normal work of the communication of the I2C bus again. According to the method for solving the communication deadlock of the I2C bus provided by the invention, no additional circuits are added, no additional cost is increased, the method for solving the communication deadlock of the I2C bus is applicable to any slave, the problem of deadlock can be rapidly and accurately solved, and no adverse effect can be brought for the normal operation of equipment.

Description

technical field [0001] The invention belongs to the technical field of system bus communication, in particular to an I 2 C bus communication deadlock solution. Background technique [0002] I 2 The C (Inter-Integrated Circuit) bus is a type of synchronous communication used to connect microcontrollers and their peripherals. I 2 The C bus has two signal lines, an SCL clock line and a bidirectional SDA data line. I 2 The C bus has the advantages of less interface lines, simplified control methods, small device packaging, and high communication speed. Under normal circumstances, I 2 The C bus protocol can guarantee the normal read and write operations of the bus, but when the I 2 C host reset (soft reset of the system, watchdog action, abnormal power supply on the board leads to reset chip action, manual button reset, etc.) and other abnormal conditions may cause I 2 The C bus deadlock occurs, which is manifested as the SCL clock line is high, and the SDA data line is a...

AI Technical Summary

Problems solved by technology

The above invention patents, if I 2 When multiple master devices and multiple slave devices are connected to the C bus, multiple reset lines for detecting reset signals need to be added, which not only increases the cost of the system, but also increases the complexity of the signal of the entire device

The invention patent application document with application number 201010606296.3 discloses a method for eliminating I 2 The device and method of C bus deadlock, this eliminates I 2 The device for C bus deadlock includes a detection unit, a clock unit, and N controllable switches; the detection unit also includes a first detection unit and a second detection unit; the detection unit detects that SCL is at a high level and SDA is at a low level When the duration exceeds the first threshold, the output trigger control signal is sent to the clock unit; the clock unit generates a clock signal according to the signal output by the detection unit, and outputs the clock signal to the I 2 The clock line SCL in the C bus; the detection unit detects that the time when SCL is at a low level exceeds the second threshold, and disconnects the device from the I 2 connection of the C bus to find the failed device and isolate the failed device from the I 2 C bus; the above-mentioned invention patent application documents still need to add multiple peripheral devices, and need to contact deadlock through external devices, which not only complicates signal processing, but also increases costs

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