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Timing sequence control method for NUMA (non-uniform memory access)-based physical multi-partition computer architecture

A technology of timing control and architecture, applied in the computer field, can solve problems such as multiple system failures and affect system reliability, and achieve the effect of ensuring reliability

Inactive Publication Date: 2012-06-27
LANGCHAO ELECTRONIC INFORMATION IND CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

Once there is a problem with any group of clock signals, timing control signals, DC power or reset signals in the hardware platform, multiple systems running on it will all fail, which greatly affects the reliability of the entire system

Method used

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  • Timing sequence control method for NUMA (non-uniform memory access)-based physical multi-partition computer architecture
  • Timing sequence control method for NUMA (non-uniform memory access)-based physical multi-partition computer architecture
  • Timing sequence control method for NUMA (non-uniform memory access)-based physical multi-partition computer architecture

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Embodiment Construction

[0021] The method of the present invention is described in detail below with reference to the accompanying drawings.

[0022] The timing control method of the NUMA-based physical multi-partition computer architecture of the present invention, the system is divided into a plurality of independent multiprocessor systems or coupled into a complete computer system, and the Legacy IO controller adopts different timing control methods; In a partitioned system, the timing is controlled by the Legacy IO controller of each partition; in a computer system where multiple partitions are coupled into a computer system, the system has and only one Legacy IO controller is effective, responsible for controlling the timing control of the entire system, of which:

[0023] 1） The timing control steps of the system divided into multiprocessor systems are as follows:

[0024] (1) Set the Legacy IO controller of the partition through the system management unit, and activate the Legacy IO controlle...

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Abstract

The invention provides a timing sequence control method for a NUMA (non-uniform memory access)-based physical multi-partition computer architecture. The novel computer architecture is characterized in that multiple processors and IO (input / output) resources of a computer system can be partitioned on a physical layer, so that the multiprocessor computer system is partitioned into a plurality of standalone multiprocessor systems, and the partitioned multiprocessor systems can also be coupled to one integral computer system. The timing sequence control method is characterized in that a plurality of standalone power source systems and clock systems in a physical multi-partition computer are set up, Legacy IO controllers are used to control the system to power on with timing sequence and realize clock enable, and the system is partitioned into a plurality of standalone multiprocessor systems or the multiprocessor systems are coupled to one integral computer system according to reset signals. The Legacy IO controllers also adopt different timing sequence control methods.

Description

technical field [0001] The present invention relates to the field of computer technology, in particular to a timing control method based on NUMA-based physical multi-partition computer architecture. Background technique [0002] Ordinary NUMA or SMP multiprocessor architecture usually only has a unified timing, clock, power supply, and reset system. Even if virtualization technology is used to implement a multi-system architecture, each system also uses a hardware platform and only has a set of fixed timing, clock, power supply, and reset systems. Once there is a problem with any group of clock signals, timing control signals, DC power or reset signals in the hardware platform, multiple systems running on it will all fail, which greatly affects the reliability of the entire system. [0003] The following is a general NUMA or SMP multiprocessor architecture diagram. Contents of the invention [0004] The purpose of the present invention is to provide a timing control meth...

Claims

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Application Information

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IPC IPC(8): G06F15/16G06F1/04
Inventor 李博乐林楷智叶丰华王欢
Owner LANGCHAO ELECTRONIC INFORMATION IND CO LTD
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