Preparation method of suspension fin

Abstract

The invention discloses a preparation method of a suspension fin. The preparation method comprises the following steps of: forming a medium layer on a semiconductor substrate; etching the medium layer and the semiconductor substrate so that at least two grooves are formed in the form of being embedded in the semiconductor substrate, and a fin is arranged between each two adjacent grooves; forming a flank by a lateral wall of the fin; etching the semiconductor substrate at the bottoms of the grooves and the fin, so as to form the suspension fin; and forming an isolation medium layer below the fin and the grooves. By using the conventional top-down process based on a reference plane, the preparation method has good compatibility with a CMOS (Complementary Metal Oxide Semiconductor) plane process and is easy to integrate.

Description

technical field [0001] The invention belongs to the technical field of semiconductors, in particular to a method for preparing a fin structure. Background technique [0002] As the integrated circuit industry continues to move forward according to Moore's law, the feature size of CMOS devices continues to shrink. Planar bulk silicon CMOS devices have encountered severe challenges, such as: severe short channel effect (SCE), source-drain leakage current, drain-induced barrier lowering effect (DIBL) and so on. In order to overcome the above problems, various new structure devices have emerged. The gate structure of the device has developed from the initial single gate to double gate (FinFET, fin transistor), multi-gate to the ring gate structure completely surrounding the channel. The gate control ability and the ability to suppress the short channel effect are continuously enhanced with the increase of the number of gates. The preparation of the above new structure devices,...

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Problems solved by technology

However, there are many problems in using SOI substrates to prepare gate-all-around devices. For example, SOI substrates have self-heating effects and floating body effects, and complex source-drain engineering is required in manufacturing to reduce source-drain parasitic resistance. Generally speaking, SOI substrates The bottom is much more expensive than ordinary bulk silicon substrates

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