Preparation method of Gate-last 1TDRAM
A single-transistor, dynamic random technology, applied in semiconductor/solid-state device manufacturing, electrical components, circuits, etc., can solve problems such as accelerating charging rate and unmanufacturable process
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Embodiment （ 1
[0027] Figure 1-Figure 4 It is a schematic process flow diagram of Embodiment 1 of the preparation method of the gate-last single-transistor DRAM of the present invention, please refer to Figure 1-4 , a method for fabricating a gate-last single-transistor dynamic random access memory, wherein,
[0028] A gate-last high dielectric constant MOS structure including a single transistor 110 is formed on a P-type silicon-on-insulator substrate through a gate-last process; the transistor 110 is set so that the source 1110 is N+ type, and the drain 1120 is N+ type , the well region 1140 is P-type, its specific structure please refer to the attached figure 1 ;
[0029] Step a: Perform wet etching to remove the sample gate in the transistor gate groove 1130 of the transistor 110 device. It should be noted that the thin oxide layer 1131 at the bottom of the transistor gate groove 1130 needs to be retained during the etching process.
[0030] Step b: perform oblique ion ...
Embodiment （ 2
[0033] Figure 5-Figure 8 It is a schematic diagram of the process flow of Embodiment 2 of the preparation method of the gate-last single-transistor DRAM of the present invention, please refer to Figure 5-Figure 8 , a fabrication method of gate-last transistor dynamic random access memory, wherein,
[0034] A gate-last high dielectric constant MOS structure including a single transistor 110 is formed on a P-type silicon substrate through a gate-last process; the transistor 110 is set so that the source 1110 is N+ type, the drain 1120 is N+ type, and the well Area 1140 is P type, its specific structure please refer to the attached Figure 5 ;
[0035] Step a: Perform wet etching to remove the sample gate in the transistor gate groove 1130 of the transistor 110 device. It should be noted that the thin oxide layer 1131 at the bottom of the transistor gate groove 1130 needs to be retained during the etching process.
[0036]Step b: Perform bidirectional symmetrical inc...
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