Semiconductor package and manufacturing method thereof
A semiconductor, stack packaging technology, applied in semiconductor/solid-state device manufacturing, semiconductor devices, semiconductor/solid-state device components, etc., can solve problems such as semiconductor packaging reliability degradation
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[0019] Exemplary embodiments of the present inventive concept will be described in more detail below with reference to the accompanying drawings. However, the inventive concept may be embodied in different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the inventive concept to those skilled in the art.
[0020] The terms used in this specification are for describing the specific embodiments only, and are not intended to limit the inventive concept. Expressions used in the singular include plural expressions unless they have clearly different meanings in context. In this specification, it will be understood that terms such as "comprising" or "having" are intended to indicate the presence of features, numbers, steps, actions, components, parts or combinations thereof disclosed in this specification, and are not inten...
Embodiment approach 1
[0023] Figure 1A to Figure 1K is a cross-sectional view illustrating a method of manufacturing a semiconductor package according to an embodiment of the present inventive concept. Figure 1L is a perspective view of a heat dissipation layer in a method of manufacturing a semiconductor package according to another embodiment of the inventive concept.
[0024] refer to Figure 1A , the second semiconductor chip (chip) 200 may be stacked on the first semiconductor chip 100 . The carrier 90 may be provided to easily handle the first and second semiconductor chips 100 and 200 and reduce warpage and / or damage. As one example, the first semiconductor chip 100 may be mounted on the carrier 90 with the adhesive layer 95 interposed therebetween and the second semiconductor chip 200 may be stacked on the first semiconductor chip 100 . Carrier 90 may include silicon, metal, glass, and the like.
[0025] The first semiconductor chip 100 and the second semiconductor chip 200 may be the ...
no. 2 approach
[0060] Figure 2A to Figure 2F is a cross-sectional view illustrating a method of manufacturing a semiconductor package according to some embodiments of the inventive concept. Figure 2G with Figure 2H is a perspective view of a heat dissipation layer in a method of manufacturing a semiconductor package according to some embodiments of the inventive concepts.
[0061] refer to Figure 2A , the first semiconductor chip 100 may be mounted on the carrier 90 with the adhesive layer 95 interposed therebetween and the second semiconductor chip 200 may be stacked on the first semiconductor chip 100 . An underfill layer 250 surrounding the conductive bumps or solder balls 210 may be formed between the first semiconductor chip 100 and the second semiconductor chip 200 . The planarization molding layer 350 may be formed by forming and planarizing the resin layer 300 (shown in dashed lines). The top surface 200s of the second semiconductor chip 200 may be as Figure 1B The non-acti...
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