Optimization method for time delay and area of fixed-polarity Reed-Muller circuit
A fixed polarity, circuit delay technology, applied in electrical digital data processing, special data processing applications, instruments, etc., can solve problems such as exhaustive search strategies and difficult to optimize results
Inactive Publication Date: 2014-02-05
HANGZHOU MAEN TECH
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Problems solved by technology
When optimizing small and medium-sized circuits, exhaustive algorithms can be used to traverse and check each polarity, but for larger-scale circuits, due to the sharp increase in the polarity space, exhaustive search strategies are difficult to obtain optimization results in a limited time
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Embodiment
[0047] Embodiment: A method for optimizing the time delay and area of a fixed-polarity Reed-Muller circuit. According to the characteristics of the fixed-polarity Reed-Muller expression, the polarity expression is simplified by using an algebraic method; then based on the delay and The area model uses the delay decomposition to calculate the delay and area of the fixed polarity Reed-Muller circuit, and integrates the two to obtain the polarity fitness function; then establishes the corresponding relationship between the fixed polarity and the particle swarm individual, and combines the list technology, Using the particle swarm optimization algorithm to search for the optimal delay and surface positivity of the fixed-polarity Reed-Muller circuit; the specific steps are:
[0048] 1) Select the evolutionary algebra as 120 generations, read it into the circuit, and express it as a function n is the function f(x n-1 , x n-2 ,...,x k ,...,x 0 ), (x n-1 , x n-2 ,...,x k ,...
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The invention discloses an optimization method for time delay and an area of a fixed-polarity Reed-Muller circuit, which is characterized by comprising the steps of simplifying a polarity expression through an algebraic method according to the characteristics of fixed-polarity Reed-Muller expression; calculating the time delay and area of the fixed-polarity Reed-Muller circuit based on a time delay and area module by means of time delay decomposition, and synthesizing the calculated time delay and area to obtain a function of polarity fitness; and building corresponding relationships between the fixed polarities and individuals of a particle swarm, referring to a list technology and performing polarity searches of optimum time delay and area of the fixed-polarity Reed-Muller circuit by means of a particle swarm optimization algorithm. Tests of Microelectronics Center of North Carolina (MCNC) Benchmark Circuit show that the optimization method for time delay and the area of the fixed-polarity Reed-Muller circuit has good optimization effects on large-scale fixed-polarity Reed-Muller circuits.
Description
technical field [0001] The invention relates to a method for optimizing a circuit, in particular to a method for optimizing the time delay and area of a fixed-polarity Reed-Muller circuit. Background technique [0002] Reed-Muller (RM) logic based on AND / XOR or OR / XNOR operations is another circuit expression method different from Boolean logic. Studies have shown that compared with Boolean logic, some circuits based on RM logic (such as arithmetic circuits, parity circuits and other functional circuits) have a more compact structure [1] and better testability [2] . RM circuit delay and area optimization is an important part of circuit synthesis and optimization technology, and has received widespread attention from the academic community. [3-6] . The n-variable RM logistic function has 2 n fixed polarity, corresponding to 2 n Different Fixed-Polarity Reed-Muller (FPRM) expressions [4] . Each expression is different, and the delay and area of the corresponding ci...
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IPC IPC(8): G06F17/50
Inventor 汪鹏君王振海
Owner HANGZHOU MAEN TECH