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Method and system for large-scale integrated circuit channel wiring based on parallel computation

A large-scale integrated circuit, parallel computing technology, applied in computing, electrical digital data processing, special data processing applications, etc., to achieve the effect of solving the problem of interconnect crosstalk

Active Publication Date: 2012-08-01
SHANGHAI FUDAN MICROELECTRONICS GROUP
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  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

Therefore, traditional routing tools must consider crosstalk optimization when dealing with circuit design for these manufacturing processes

Method used

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  • Method and system for large-scale integrated circuit channel wiring based on parallel computation
  • Method and system for large-scale integrated circuit channel wiring based on parallel computation
  • Method and system for large-scale integrated circuit channel wiring based on parallel computation

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Embodiment Construction

[0032] Preferred embodiments of the present invention will be described in detail below in conjunction with the accompanying drawings.

[0033] This embodiment designs a channel routing method for large-scale integrated circuits based on parallel computing. The channel routing problem on different layers is divided into channel routing sub-problems in each routing unit row, and then these sub-problems are abstracted into a series of The linear allocation problem inside the routing unit. The object to be allocated in this problem is the wiring segment of different nets inside the wiring unit, and the allocated containers are different routing channels, such as figure 1 shown. This method is based on a distributed computing framework. For the channel routing sub-problem to be processed, it is processed in parallel by multi-threading, such as figure 2 shown. For the linear allocation problem inside each routing unit, this method optimizes these objectives by minimizing the al...

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Abstract

The invention discloses a method and a system for large-scale integrated circuit channel wiring based on parallel computation, and belongs to the field of integrated circuit design. The method comprises the steps as follows: dividing channel wiring problems on different layers into channel wiring sub-problems in each routing unit row, and abstracting the channel wiring sub-problems into a series of linear distribution problems in the routing units for computing; based on a distributed computation framework, carrying out multi-thread parallel processing on the channel wiring sub-problems to be solved; and optimizing the targets through the minimize distribution expense in the linear distribution problems in the routing units by modeling congestion degree, time delay and crosstalk parameters. According to the invention, the ultra-large-scale integrated circuit channel wiring problem can be quickly and effectively processed, and the interconnection crosstalk problem of process nodes with interconnection line width of 65 nm and below can be solved at the same time.

Description

technical field [0001] The invention belongs to the field of integrated circuit design, in particular to the technical category of integrated circuit design optimization under the integrated circuit manufacturing process with the line width of the interconnection line at or below 65nm. Background technique [0002] The integrated circuit is designed by the designer with the help of electronic design automation (EDA) tools to design the integrated circuit layout, delivered to the integrated circuit manufacturer, through the circuit mask preparation (Mask), and the wafer (Wafer) for oxidation, doping, photolithography A series of manufacturing processes such as transferring the circuit mask to the wafer, so as to realize its circuit function. For digital circuit design, the layout design process includes steps such as behavioral synthesis, logic synthesis, physical design and layout optimization. Among them, physical design is the most time-consuming step and has the greatest...

Claims

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Application Information

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IPC IPC(8): G06F17/50
Inventor 李卓远陈刚
Owner SHANGHAI FUDAN MICROELECTRONICS GROUP
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