Preparation method of MOS transistor

Abstract

The invention provides a preparation method of an MOS transistor, comprising: providing a semiconductor substrate, wherein a well region and a shallow-slot isolation structure are formed in the semiconductor substrate; carrying outchannel ion injection in the well region of the semiconductor substrate to form a channel injection region; forming a grid structure on the semiconductor substrate; carrying out a bag-like region ion injection and a lightly doped source / drain region(LDD) large angle inclined ion injection, wherein the grid structure is used as a mask; carrying out a first rapid thermal annealing process to form the bag-like region and the lightly doped source / drain region; forming side walls on two sides of the grid structure; and carrying out a source / drain ion injection and a second rapid thermal annealing process to form source / drain regions, wherein the grid structure and the side walls are used as masks. According to the preparation method of the invention, an ultra-shallow junction MOS transistor with longer effective channels is formed through the LDD large angle inclined ion injection. Thus, HCI effects can be inhibited, SCE effects can be substantially improved, and junction electric leakage can be decreased.

Description

technical field [0001] The invention relates to the field of semiconductor manufacturing, in particular to a method for manufacturing a MOS transistor. Background technique [0002] With the advancement of the semiconductor industry, the feature size and depth of semiconductor devices continue to shrink, especially when entering the node of 65 nanometers and below, requiring the source / drain region and the source / drain extension region (Source / DrainExtension) to become shallower accordingly, and the junction The doped junction with a depth below 100nm is usually called an ultra-shallow junction (USJ). The ultra-shallow junction can better improve the short-channel effect of the device, but with the further improvement of the device size and performance, the junction leakage phenomenon is a super-shallow junction. Shallow knot technology increasingly needs to solve problems. [0003] In the prior art, As, Ge, and C ions are usually implanted in sequence to form a lightly dop...

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Problems solved by technology

When this method uses Ge ion implantation to eliminate the short channel effect caused by As ion implantation, it is easy to produce transient enhanced diffusion effect (TED), resulting in the degradation of short channel device characteristics and greater junction leakage; C ion implantation eliminates Ge as an important component. The defects caused by ion implantation will degrade the electrical activation of As ions and cause increased junction leakage (hot carrier injection effect, HCI), so the ultra-shallow junction formed by this method is still difficult to achieve SCE (short channel effect ) and RSCE (reverse short channel effect) control and lower junction leakage performance

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