Design method and system for space-borne FPGA preventing space environment influence

A technology of space environment and design method, applied in the field of spaceborne FPGA, can solve problems such as single-event flipping, and achieve the effect of convenient and reliable anti-space environment influence

Inactive Publication Date: 2012-09-26
SHANGHAI SATELLITE ENG INST
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Problems solved by technology

[0004] In order to solve the problem of single event flipping of XILINX FPGA, the information processor of polar orbit meteorological satellite data transmission system, the present invention proposes a space-borne FPGA design method and system to prevent the impact of space environment. Using the present invention, it is convenient and reliable to realize the anti-space environment Impact on Onboard FPGA Design

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  • Design method and system for space-borne FPGA preventing space environment influence
  • Design method and system for space-borne FPGA preventing space environment influence

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Embodiment Construction

[0014] The embodiments of the present invention are described in detail below. Based on the premise of the technical solution of the present invention, the present embodiment provides detailed implementation and specific operation process, but the protection scope of the present invention is not limited to the following embodiments. Technical means that are not described in detail in the following embodiments can be implemented by using existing technologies or conventional technologies.

[0015] Such as figure 1 Shown is a functional block diagram of an on-board FPGA designed to prevent the influence of the space environment in an embodiment of the present invention. As shown in the figure, among them: XILINX FPGA 1, ACTEL FPGA2, PROM 3. When designing, read the configuration file of XILINX FPGA directly to ACTEL FPGA through the JTAG port, and ACTEL FPGA will check the configuration file. Once an error is found and checked, it will independently control the PROM to redo the...

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Abstract

The invention relates to a design method and a system for space-borne FPGA preventing space environment influence, comprising XIL INX FPGA, ACTEL FPGA and PROM. Sum check is carried out to configuration files by ACTEL FPGA, and configuration files of XIL INX FPGA to ACTEL FPGA by JTAG port are read. Once an error is discovered during the sum check, loading is again carried out to configuration files of XIL INX FPGA that overturning by autonomously control PROM, so that correctness of configuration files in XIL INX FPGA is guarantied. Occurrence of single particle event can be rapidly detected by adopting the method, and influence caused by the single particle event can be lowered to lowest. The design method has been verified in information processor of FY-3satellite data transmission subsystem.

Description

technical field [0001] The invention relates to a space-borne FPGA, more specifically, to a space-borne FPGA design method and system for preventing the impact of the space environment. Background technique [0002] my country's new-generation polar-orbiting meteorological satellite Fengyun-3 is my country's second-generation polar-orbiting meteorological satellite, which is used to achieve global, all-weather, three-dimensional, quantitative remote sensing. The information processor of the digital transmission system mainly completes the functions of format arrangement, data encryption, scrambling and encoding of multiple satellite payload data, and is one of the core stand-alone satellites. The orbital altitude of the satellite is about 830Km, and the space environment is relatively harsh, especially the influence of single particles is more prominent. The main function of the information processor is realized by XILINX FPGA. Due to the problem of the production process o...

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H03K19/177
Inventor 刘波史琴郭强
Owner SHANGHAI SATELLITE ENG INST
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