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On-chip network node communication method based on macro virtual channel

A communication method and network-on-chip technology, applied in the direction of data exchange network, digital transmission system, electrical components, etc., can solve problems such as limited address space, susceptibility to electromagnetic interference, scalability problems, etc., and achieve the effect of solving information transmission errors

Inactive Publication Date: 2012-10-10
HEILONGJIANG UNIV
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0002] With the development of integrated circuits, there are three major problems in the system-on-chip (SoC, System on Chips) based on traditional bus interconnection: the scalability problem caused by limited address space, the communication efficiency problem and the area and area caused by global synchronization. power consumption problem
However, in the deep sub-micron stage, due to the shrinking chip size and the gradually increasing number of devices, data packets are more susceptible to electromagnetic interference during the transmission of the network on chip, resulting in errors such as single event flips.

Method used

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  • On-chip network node communication method based on macro virtual channel
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  • On-chip network node communication method based on macro virtual channel

Examples

Experimental program
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specific Embodiment approach 1

[0007] Specific implementation mode one: the following combination figure 2 This embodiment will be specifically described. This embodiment is realized through the following process: one, from another data packet of communication node, enters this communication node router; data packet; two copies of backup data packets are copied for reliability requirements data packets; two, two copies of backup data packets of reliability requirements data packet and its duplication enter three virtual channels of input register ICL respectively; meanwhile, reliable The reliability requirement data packet and the two backup data packets it replicates send an application signal to the virtual channel allocator VCA. If the application is approved, the reliability requirements data packet and the two backup data packets it replicates enter the macro virtual channel MVC respectively. , in the macro-virtual channel MVC, according to the principle that the minority is subject to the majority, ...

specific Embodiment approach 2

[0009] Specific implementation mode two: the following combination figure 1 with figure 2 This embodiment will be specifically described. The difference between this embodiment and Embodiment 1 is: in step 2, when the data packet has reliability requirements, the virtual channel allocator VCA checks the status of the three virtual channels of the macro virtual channel, if they are idle, release For the locking of the macro-virtual channel, complete the three-mode redundancy judgment of the reliability-required data packet and the two backup data packets copied in the macro-virtual channel MVC; if the status of the three virtual channels is not idle, return None Channel allocation command, lock the three virtual channels of the macro-virtual channel, and wait for the three virtual channels to be idle at the same time before allocating the macro-virtual channel;

[0010] When the data packet has no reliability requirement, the virtual channel allocator VCA checks whether the ...

specific Embodiment approach 3

[0015] Specific implementation mode three: the following combination image 3 This embodiment will be specifically described. The difference between this embodiment and embodiment two is that in step two, the data packet with reliability requirements arrives at the microchip accepting port SII of the input channel, then enters the latch channel PIV, and passes through the signal line 1-2 to the virtual channel The controller VCA applies for a virtual channel, and the virtual channel allocator VCA checks the status of the three virtual channels of the macro virtual channel VCA; if they are idle, the latch channel PIV unlocks the macro virtual channel VCA, and sends data packets with reliability requirements Transmission and three-mode redundancy judgment; if the macro-virtual channel VCA is not idle, return no virtual channel to allocate, and the latch channel PIV locks the three virtual channels of the macro-virtual channel, and waits for the three virtual channels to be idle ...

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Abstract

The invention discloses an on-chip network node communication method based on a macro virtual channel, and relates to the field of the communication methods between on-chip network nodes, so that information transmission errors caused by the errors of input caches inside the communication nodes are avoided. The method is realized through the following process that a data packet from another communication node enters a route of a communication node; two copies of the data packets with a reliability requirement are prepared; the data packets with the reliability requirement and the two copies of backup data thereof respectively enter virtual channels of the input caches; the data packets with the reliability requirement and the two copies of backup data thereof send application signals to a virtual channel distributor; if the application is approved, the data packets with the reliability requirement and the two copies of backup data thereof respectively enter the macro virtual channel; in the macro virtual channel, a principle that the minority is subordinate to the majority is followed and a correct data packet is determined; the macro virtual channel is a virtual channel of three specified addresses in the input caches; and the obtained correct data packet is transmitted to the next communication node through an output channel.

Description

technical field [0001] The invention relates to a communication method between nodes of an on-chip network. Background technique [0002] With the development of integrated circuits, there are three major problems in the system-on-chip (SoC, System on Chips) based on traditional bus interconnection: the scalability problem caused by limited address space, the communication efficiency problem and the area and area caused by global synchronization. power consumption problem. Network on Chip (NoC, Network on Chips) attempts to solve these problems from the architecture, and will become the mainstream design technology of the next generation of integrated circuits. However, in the deep sub-micron stage, due to the shrinking chip size and increasing number of devices, data packets are more susceptible to electromagnetic interference during the transmission of the network on chip, resulting in errors such as single event flips. Alpha particles emitted by trace amounts of uranium...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H04L12/56
Inventor 王嘉芳李本娟
Owner HEILONGJIANG UNIV
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