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Method and system for jump instruction encoding

A technology of jump instructions and instructions, applied in the field of processors, can solve the problems of lack of adaptability and many hardware resources, and achieve the effects of saving hardware logic and hardware resources, simplifying hardware logic, saving area and cost

Inactive Publication Date: 2017-10-24
ZTE CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

This scheme also needs to increase hardware logic. For loop nesting, more hardware resources are needed, and if the number of loop body instructions is less than N (N represents the number of weeks required to fetch instructions from MEMORY), this scheme is not adaptable. sex

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Embodiment Construction

[0029] Since it takes N cycles to fetch the LOOP_BEGIN instruction from MEMORY when looping back, if you start to fetch instructions from MEMORY after waiting for the LOOP_END instruction, then the pipeline must stop for N cycles, and the performance loss is great. In order to avoid this loss, you can fetch instructions from MEMORY N cycles in advance in the hardware, so that when LOOP_END is executed, the instructions of LOOP_BEGIN have also been fetched from MEMORY, so that PIPELINE does not need to pause.

[0030] The above-mentioned solution can be realized by an assembly compiler (ASS). ASS can encode the assembly instructions written by the programmer into binary or hexadecimal. When ASS is coding, the LOOP_END flag can be advanced by N weeks (this cycle is the operation cycle from LOOP_BEGIN to LOOP_END) to generate the required execution file exe.bin. When the exe.bin instruction is executed, the hardware can see LOOP_END N weeks in advance, so that the instruction ca...

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Abstract

The invention discloses a method and system for encoding a jump instruction, which can obtain the cycle start instruction in memory in advance relative to the operation cycle when the loop is executed; when the last instruction of the loop body is executed, the cycle start instruction is completed of acquisition. The method and system of the present invention simplifies the hardware logic from the software level through the preprocessing of the assembly code, ensuring that there is no need to add additional logic to solve the problem that the pipeline needs to stop when the loop is turned back, and saves a lot of hardware logic and hardware. resources, saves area and cost, makes implementation simple, and improves the reliability of the implementation solution.

Description

technical field [0001] The invention relates to the field of processors, in particular to a jump instruction encoding method and system. Background technique [0002] At present, one of the reasons for processor performance loss may be the execution of loop instructions. A loop body contains N instructions, which need to be repeatedly executed many times. The last instruction of the loop body can be represented by LOOP_END. When LOOP_END is seen in the decoding stage of PIPELINE (instruction pipeline), if LOOP_BEGIN (the first instruction of loop body) is taken from MEMORY (memory) at this time, PIPELINE must stop Waiting for MEMORY, the waiting period depends on the speed and architecture of MEMORY. For common processors, the frequency of use of loop instructions is very frequent, so the performance loss caused by such overhead is very large. There are two existing solutions. The first is to add LOOP_BUFFER (circular buffer). When the loop body is executed for the first t...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G06F9/32
CPCG06F9/30065G06F9/3804
Inventor 黎立煌保罗帕瓦旺萨克曹庆新
Owner ZTE CORP