High-accuracy fine adjustment method for charge coupled device (CCD) video signal sampling timing sequence

Abstract

The invention discloses a high-accuracy fine adjustment method for a charge couple device (CCD) video signal sampling timing sequence, and belongs to the technical field of CCD detector imaging designs. The method comprises the following steps that: an input clock of a field programmable gate array (FPGA) is connected to a digital clock manager 1 (DCM1) through a global clock input buffer (IBUFG), and a clock outputted by a clock 0 (CLK0) end is driven by a global clock buffer (BUFG) to acquire a system clock SysClk; the DCM1 locks a state marking signal, and after being inverted and latched by a two-stage D flip flop, the state marking signal serves as a reset signal of a DCM2; the SysClk is connected to the clock input (CLKIN)end of the DCM2, and a clock outputted by the CLK0 output end is driven by the BUFG to acquire a correlated double sampling clock CdsClk, and the CdsClk is connected to the feedback clock end CLKFB of the DCM2; and dynamic adjustment control of the phase relationship between the CdsClk and the SysClk is realized by a TimingCon module. By the method, the sampling timing sequence of the video signals of the CCD can be finely adjusted with high accuracy, adjustment accuracy can be improved to magnitude of dozens of picoseconds, and the problem that the best timing sequence position cannot be sampled in the conventional design method is solved.

Description

technical field [0001] The invention belongs to the technical field of CCD detector imaging design, and in particular relates to a method for fine-tuning sampling timing of high-precision CCD video signals. Background technique [0002] The CCD detector imaging system generally consists of an optical-mechanical system, a pre-amplification circuit board and a signal processing circuit board. Among them, the pre-amplification circuit board contains CCD detector and pre-amplification circuit, the signal processing board contains imaging controller, timing driver and video signal processing circuit, and the CCD video signal is introduced into the signal processing circuit board by the pre-amplification circuit board through the coaxial cable , whose structure is as figure 1 shown. [0003] The detector adopts the visible light TDI-CCD of Dalsa Company, and the pixel readout frequency is up to 40MHz. The imaging controller adopts the FPGA chip of Virtex-II Pro series of Xilinx...

AI Technical Summary

Problems solved by technology

In the actual development process, in some cases, the adjustment accuracy of the above two design methods cannot meet the demand, and the flexibility of timing adjustment is poor

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