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Method for manufacturing array substrate, array substrate and display device

An array substrate and substrate technology, which is used in semiconductor/solid-state device manufacturing, instruments, semiconductor devices, etc., can solve the problems of abnormal display of pixel electrodes 6, steep gradient angles of step differences, and defective pixel electrode faults, so as to solve abnormal display and avoid abnormal display. severing effect

Active Publication Date: 2012-10-24
BOE TECH GRP CO LTD +1
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0008] from figure 2 It can be seen from the figure that in the array substrate with such a structure, the pixel electrode 6 in the pixel area has a section 10, because the section difference is too large and the slope angle (Profile) is too steep, there is a serious phenomenon of pixel electrode disconnection (disconnect) , and the fault of the pixel electrode 6 will cause abnormal display

Method used

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  • Method for manufacturing array substrate, array substrate and display device
  • Method for manufacturing array substrate, array substrate and display device
  • Method for manufacturing array substrate, array substrate and display device

Examples

Experimental program
Comparison scheme
Effect test

Embodiment 1

[0099] refer to image 3 , the array substrate of the embodiment of the present invention may include:

[0100] Substrate 1;

[0101] A gate electrode and a gate line formed by a gate metal layer on the substrate 1 (not shown in the figure);

[0102] a gate insulating layer 3 located on the substrate 1 formed with the gate electrode and the gate line;

[0103] an active layer 4 located on the gate insulating layer 3;

[0104] A source electrode (not shown in the figure), a drain electrode 5 and a data line (not shown in the figure) located on the active layer 4;

[0105] A pixel electrode 6 with a step portion 10 located on the substrate 1 formed with the source electrode, the drain electrode 5 and the data line, the pixel electrode 6 is connected to the drain electrode 5;

[0106] a passivation layer 7 located on the substrate 1 on which the pixel electrode 6 is formed, and a first via hole 11 and a second via hole 12 are formed on the passivation layer 7;

[0107] A com...

Embodiment 2

[0126] refer to Figure 4 , the array substrate of the embodiment of the present invention may include:

[0127] Substrate 1;

[0128] A gate electrode and a gate line formed by a gate metal layer on the substrate 1 (not shown in the figure);

[0129] a gate insulating layer 3 located on the substrate 1 formed with the gate electrode and the gate line;

[0130] an active layer 4 located on the gate insulating layer 3;

[0131] A source electrode (not shown in the figure), a drain electrode 5 and a data line (not shown in the figure) located on the active layer 4;

[0132] A pixel electrode 6 with a step portion 10 located on the substrate 1 formed with the source electrode, the drain electrode 5 and the data line, the pixel electrode 6 is connected to the drain electrode 5;

[0133] a passivation layer 7 located on the substrate 1 on which the pixel electrode 6 is formed, a third via hole 13 is formed on the passivation layer 7, and the third via hole 13 straddles the leve...

Embodiment 3

[0138] refer to Figure 5 , the array substrate of the embodiment of the present invention may include:

[0139] Substrate 1;

[0140] A gate electrode (not shown in the figure), a gate line (not shown in the figure) and a second connection part 2 formed by a gate metal layer on the substrate 1, the second connection part 2 is connected to the gate electrode and the gate line disconnected;

[0141] a gate insulating layer 3 located on the substrate 1 on which the gate electrode, gate line and second connecting portion 2 are formed, and a fourth via hole 14 and a fifth via hole 15 are formed on the gate insulating layer 3;

[0142] an active layer 4 located on the gate insulating layer 3;

[0143] A source electrode (not shown in the figure), a drain electrode 5 and a data line (not shown in the figure) located on the active layer 4;

[0144] A pixel electrode 6 with a step portion 10 located on the substrate 1 formed with the source electrode, the drain electrode 5 and the...

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Abstract

The invention provides a method for manufacturing an array substrate, the array substrate and a display device and belongs to the field of liquid crystal display. The array substrate comprises a pixel electrode provided with a segment difference portion, wherein parts of the pixel electrode located on two sides of the segment difference portion are communicated through conducting layers and through via holes, and the conducting layers and the pixel electrode are located on different layers. Shutoff of a pixel electrode layer signal caused by fault of the pixel electrode can be avoided.

Description

technical field [0001] The invention relates to the field of liquid crystal display, in particular to a method for manufacturing an array substrate, the array substrate and a display device. Background technique [0002] Thin film transistor liquid crystal display (TFT-LCD) has the characteristics of small size, low power consumption, and no radiation, and occupies a dominant position in the current flat panel display market. Among them, ADvanced Super Dimension Switch (ADS for short) uses the electric field generated by the edge of the slit electrode in the same plane and the electric field generated between the slit electrode layer and the plate electrode layer to form a multi-dimensional electric field, so that the liquid crystal All oriented liquid crystal molecules between the slit electrodes in the cell and directly above the electrodes can be rotated, thereby improving the working efficiency of the liquid crystal and increasing the light transmission efficiency. Adva...

Claims

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Application Information

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IPC IPC(8): H01L27/02H01L29/786H01L21/77G02F1/1362G02F1/1368
CPCG02F1/1362G02F1/136227G02F1/1368
Inventor 董向丹玄明花高永益黄炜赟
Owner BOE TECH GRP CO LTD
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