Low-pressure-difference linear stabilizer

Abstract

A low-pressure-difference linear stabilizer comprises an error amplifier, a buffer, a first bypass P-type MOS (metal oxide semiconductor) transistor, a first resistor, a second resistor, a series resistor, a series capacitor and a voltage conversion rate increasing circuit. An output end of the error amplifier is connected to an input end of the buffer BF, an output end of the buffer BF is connected to a grid of the first bypass P-type MOS transistor, and a drain of the first bypass P-type MOS transistor serves as an output end of the low-pressure-difference linear stabilizer. The voltage conversion rate increasing circuit comprises a second bypass P-type MOS transistor, a first attachment NMOS (n-channel metal oxide semiconductor) transistor, a second attachment PMOS (p-channel metal oxide semiconductor) transistor, a third attachment PMOS transistor, a third attachment NMOS transistor, a second attachment NMOS transistor and a second current source. By the aid of the low-pressure-difference linear stabilizer, voltage conversion rate can be effectively increased without increasing power consumption. Therefore, the low-pressure-difference linear stabilizer is particularly applicable to low-power-consumption applications with the requirement on quick current load response.

Description

technical field [0001] The invention relates to the field of semiconductor circuit design, more specifically, the invention relates to a low-dropout linear regulator. Background technique [0002] Low dropout linear regulator LDO (low dropout regulator) is a power conversion chip relative to traditional linear regulators. Traditional linear regulators require the input voltage to be higher than the output voltage by more than 2v ~ 3V, otherwise they will not work properly. However, in some cases, the requirement that the input voltage is 2v to 3v higher than the output voltage cannot be met. For example, in the case of 5v input to 3.3v output, the voltage difference between input and output is only 1.7v, which is obviously not satisfied. Conditional. Aiming at this situation, a low-dropout linear regulator LDO-like power conversion chip is proposed. [0003] figure 1 A block diagram of a low dropout linear regulator according to the prior art is schematically shown. [...

AI Technical Summary

Problems solved by technology

According to the traditional low-dropout linear regulator, if you want to achieve a larger voltage conversion rate, you must increase the current of the buffer, resulting in greater power consumption

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