Assembly line type D/A convertor capable of calibrating capacitance mismatch and finite gain error

An analog-to-digital converter, a pipelined technology, applied in the direction of analog/digital conversion, code conversion, analog/digital conversion calibration/testing, etc., can solve problems such as difficult implementation and time-consuming, and achieve the effect of improving performance

Inactive Publication Date: 2008-07-16
EMENSA TECH CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, in general, these methods are either difficult to implement, time-consuming, require additional conversion processing steps, or both

Method used

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  • Assembly line type D/A convertor capable of calibrating capacitance mismatch and finite gain error
  • Assembly line type D/A convertor capable of calibrating capacitance mismatch and finite gain error
  • Assembly line type D/A convertor capable of calibrating capacitance mismatch and finite gain error

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Embodiment Construction

[0030] The block diagram of the implementation scheme based on the present invention is shown in FIG. 4 , wherein the pipelined analog-to-digital converter adopts a structure of 1.5 bits per stage, and the resolution is 10 bits (N=10) as an example. Compared with the traditional analog-to-digital converter 100 in FIG. 1 , the new analog-to-digital converter 400 has an additional sub-conversion stage circuit 410 and a control clock generation circuit 440 . The clock input passes through the control clock generation circuit 440 to generate the required clock sequence to control the operation of each module, including the optional sample and hold circuit 401, sub-conversion stage circuits 402-410, the last full-parallel stage circuit 420 and digital correction circuit 430. Generally speaking, in addition to the last 2-bit all-parallel stage circuit, a 10-bit pipelined analog-to-digital converter also needs 8 sub-conversion stage circuits. However, in this new structure, in order...

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Abstract

The invention belongs to the analog-to-digital converter (ADC) technical field, in particular to a pipelining ADC capable of calibrating capacitance mismatch and finite gain error. Based on the prior similar ADC, the invention further adopts a sub-switching stage circuit, a clock generation control circuit and an error detector, and ensures that each sub-switching stage circuit has two operation modes, i.e. a normal operation mode and a calibration mode; meanwhile, each sub-switching stage circuit uses the same error detector to amplify the output of the sub-switching stage circuit under calibration; in addition, each sub-switching stage circuit has a storage unit storing the output of the error detector and is used to control the gain of the amplifier of the circuit of the stage; moreover, the absolute values of the two errors caused by the finite gain of the amplifier and capacitance mismatch are equal in value but opposite in symbol, thereby balancing out each other and ensuring the circuit of the stage realizes non-deviation conversion.

Description

technical field [0001] The invention belongs to the technical field of analog-to-digital converters, and in particular relates to a pipelined analog-to-digital converter using a low-gain amplifier. Background technique [0002] An analog-to-digital converter (ADC) is a component that converts an analog signal into a digital signal, that is, digitizes the analog signal. In high-speed analog-to-digital converters, the fastest reported so far is the all-parallel (flash) structure. However, an analog-to-digital converter based on a fully parallel structure requires a large number of extremely accurate and fast comparators, which will consume a large amount of chip area and power. Among the many analog-to-digital converter structures, many can overcome the shortcomings of the all-parallel structure of the analog-to-digital converter, and the pipeline structure is one of them. Moreover, the pipeline architecture provides a better trade-off between speed, accuracy, power consumpt...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H03M1/10
CPCH03M1/0695H03M1/1057H03M1/44
Inventor 陈诚袁及人
Owner EMENSA TECH CO LTD
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