Frequency control system and method applied to power factor corrector
A technology of power factor correction and frequency control, which is applied in the direction of output power conversion devices, sustainable manufacturing/processing, high-efficiency power electronics conversion, etc., can solve problems such as reducing system power factor, and achieve lower THD and lower system total harmonics Distortion, the effect of increasing the PF value
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Embodiment 1
[0072] See Picture 10 The present invention discloses a frequency control system applied to a power factor corrector. The system includes: a zero current detector ZCD (zero current detector) 40, an analog multiplier 20, an error amplifier EA (Error amplifier) 10, and a current Detection comparator 30, frequency corrector 50.
[0073] The output terminal of the error amplifier 10 is connected to an input terminal of the analog multiplier 20, the output terminal of the analog multiplier 20 is connected to an input terminal of the current detection comparator 30, and the output terminal of the current detection comparator 30 is connected to the frequency corrector 50. An input terminal, the output terminal of the zero current detector 40 is connected to an input terminal of the frequency corrector 50.
[0074] The zero current detector 40 is used to detect the boost inductance of the power factor corrector PFC ( Image 6 The current in L1), when the boost inductor current drops to ...
Embodiment 2
[0088] See Figure 13 The difference between this embodiment and the first embodiment is that in this embodiment, the frequency corrector includes an RS flip-flop 53, an adjustable timer 51, and a logical OR gate 52. The adjustable timer 51 receives the MULT voltage and the clear signal, and the clear signal comes from the output PFC power tube control signal. The output signal of the adjustable timer 51 is connected to one input terminal of the logic OR gate 52, and the output signal of the zero current detector 40 is connected to the other input terminal of the logic OR gate 52. The output signal of the logical OR gate 52 is connected to an input terminal of the RS flip-flop 53, and the output signal of the current detection comparator 30 is connected to an input terminal of the RS flip-flop 53.
[0089] See Picture 14 , The adjustable timer 51 includes a constant current source I1, a first capacitor C1, a clear switch S1 and its control input signal, a hysteresis comparator ...
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