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MPC8280 minimum system applying CPLD (complex programmable logic device) and state switching method for setting hard reset configuration words

A hard reset and minimal technology, applied in data reset devices, electrical digital data processing, instruments, etc., can solve the problems that the watchdog timing period cannot be increased, PowerPC cannot be shortened, etc., and achieve the effect of simple and reliable operation

Active Publication Date: 2015-05-13
HARBIN INST OF TECH
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0005] The present invention is to solve the problem that the existing PowerPC using CPLD cannot shorten the watchdog timing cycle and improve the flexibility of the system, and provides a minimum system of MPC8280 using CPLD and a state transition method for setting hard reset configuration words

Method used

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  • MPC8280 minimum system applying CPLD (complex programmable logic device) and state switching method for setting hard reset configuration words
  • MPC8280 minimum system applying CPLD (complex programmable logic device) and state switching method for setting hard reset configuration words
  • MPC8280 minimum system applying CPLD (complex programmable logic device) and state switching method for setting hard reset configuration words

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Experimental program
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specific Embodiment approach 1

[0039] Specific implementation mode one: the following combination figure 1 Describe this embodiment, the MPC8280 minimum system of the application CPLD described in this embodiment, it comprises MPC8280, CPLD and TPS3110, the address bus signal output pin 60x_BA[31-27] of MPC8280 and the address bus signal input pin 60x_BA of CPLD [31-27] connect;

[0040] The data bus 60x_BD[0-7] of MPC8280 is connected to the data bus 60x_BD[0-7] of CPLD;

[0041] The level signal output pin MODCK[1-3] of CPLD is respectively connected with the clock hardware configuration pin MODCK[1-3] of MPC8280;

[0042] The interrupt signal output pin IRQ1# / IRQ2# of CPLD is respectively connected with the interrupt signal input pin IRQ1# / IRQ2# of MPC8280;

[0043] The chip selection signal output terminal of MPC8280 is connected with the chip selection signal input terminal of CPLD;

[0044] The output end of the hard reset signal pin HRESET# of the MPC8280 is connected to the input end of the hard ...

specific Embodiment approach 2

[0051] Specific implementation mode two: the following combination figure 1 Describe this embodiment. This embodiment is a further description of the clock hardware configuration pin MODCK[1-3] of the MPC8280 in Embodiment 1. The clock hardware configuration pin MODCK[1-3] of the MPC8280 described in this embodiment The state of is set by the following methods:

[0052] For applications that do not need to dynamically change the working clock of the MPC8280 core and CPM, use initialization to set the state of the output to the MODCK[1-3] pin during logic design;

[0053] For applications that do not need to dynamically change the MPC8280 core but need to change the CPM working clock, reset the initial value during logic design and program it into the CPLD;

[0054] For applications that need to dynamically change the working clock of the MPC8280 core and CPM but reprogram the CPLD, the 3 bits in the internal register of the custom CPLD correspond to MODCK[1-3]. By writing dat...

specific Embodiment approach 3

[0055] Specific implementation mode three: the following combination figure 1 Describe this embodiment mode, combine below figure 1 Describe this embodiment, this embodiment is the further explanation to the MPC8280 of embodiment one to the read and write operation of CPLD internal register, the implementation method of MPC8280 described in this embodiment to the read and write operation of CPLD internal register is:

[0056] Write register, when the CPLD chip select signal CS2# and write enable signal are valid, store the value on the data line in the register at the address specified by the address bus; read register, when the CPLD chip select signal and read enable signal are valid , read the value in the register of the address specified by the address bus into the data line.

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Abstract

An MPC8280 minimum system applying a CPLD and a state switching method for setting hard reset configuration words relate to an MPC8280 minimum system. The purpose of the invention is to solve the problem that the conventional Power PC (personal computer) applying the CPLD does not shorten the watchdog timing cycle and enhance the flexibility of a system. The MPC8280 minimum system applying the CPLD comprises an MPC8280, the CPLD and a TPS3110. A state machine carrying out the state switching method for setting hard reset configuration words on the basis of the MPC8280 minimum system applying the CPLD includes a waiting state, an idle state, a first byte state, a second byte state, a third byte state, an invalid address state and a fourth byte state, and hard reset configuration words can be set by the way of the conditioned switching between the states. The minimum system and the state switching method are applicable to single-board systems.

Description

technical field [0001] The invention relates to a minimum system of MPC8280. Background technique [0002] With the development of technology, single-board systems have higher and higher performance requirements for processors. High-end processors integrate many commonly used peripheral modules. When building a single-board system, only a small number of devices can be expanded to achieve functions. It is beneficial to reduce the instability of the system. In the field of communication and high-end embedded equipment, the high-performance processor PowerPC is widely used. Here we take the MPC8280 minimum system as an example to illustrate. MPC8280 provides many functional interfaces, users need to choose flexibly according to system requirements, and correctly configure related registers and pin states when using them. [0003] For example, in the clock design of MPC8280, the peripheral bus frequency is determined by the system input clock, the communication processor modu...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G06F1/24G06F11/00
Inventor 刘大同彭宇刘连胜见其拓刘川
Owner HARBIN INST OF TECH
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