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Level shifter with balanced duty cycle

A level shifter, a technology of level shifting, applied in electrical components, devices that generate electrical pulses, and devices that give pulses at different times, etc., can solve problems such as unfavorable jitter, data errors, and distortion of signal time-domain characteristics.

Active Publication Date: 2016-10-26
QUALCOMM INC
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0004] While simple level shifters are available in the prior art that accurately and adequately translate the levels associated with an input logic signal, a disadvantage of such circuits is that they can make time-domain characteristics of the signal such as duty cycle ) distortion due to mismatched rise / fall transitions that do not correspond precisely enough to the timing characteristics of the original signal for high-speed digital communication applications
This matching, or corresponding lack thereof, can adversely cause jitter, data errors, etc.

Method used

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  • Level shifter with balanced duty cycle
  • Level shifter with balanced duty cycle
  • Level shifter with balanced duty cycle

Examples

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Embodiment Construction

[0019] Various aspects are disclosed in the following description and related drawings directed to specific embodiments. Alternative embodiments may be devised without departing from the scope of the present invention. Additionally, well-known elements will not be described in detail or will be omitted so as not to obscure the relevant details.

[0020] The word "exemplary" is used herein to mean "serving as an example, instance, or illustration." Any embodiment described herein as "exemplary" is not necessarily to be construed as preferred or advantageous over other embodiments. Likewise, the term "embodiments" does not require that all embodiments include the discussed feature, advantage or mode of operation.

[0021] The terminology used herein is for describing particular embodiments only and is not intended to be limiting of the embodiments. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms unless the context clearly dictat...

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Abstract

The present invention provides a level shifter (400) and method for balancing rise and fall times of a signal. The input circuit (420, 413) receives a differential logic signal (Inp, Inn) having two complementary logic levels. level transition balancing circuit (420) balances the rise time and fall time. A logic element (430) stores and provides an output (outp, ounn) of said level-shifted version of said logic level. The level shift balancing circuit (420) includes a capacitor (421) in parallel with a field effect transistor (422) for each input. The capacitor destabilizes the input to the logic element, and the transition is balanced using capacitance and a level previously stored in the logic element (435, 436).

Description

technical field [0001] The present invention relates to high speed receivers and related circuits, and more particularly, to latch-based level shifters with balanced rise and fall times. Background technique [0002] Digital circuits typically use consistent logic levels for internal signals. However, the logic levels may vary from system to system, and even within various subsystem circuits within the same system. Level shifters can be used to interface digital circuits that use one logic level to digital circuits that use another logic level. Multiple level shifters may be used, such as one in each system where bi-directional shifting is required. For example, the driver can transition from internal logic levels to levels compatible with standard interface line levels. For example, line receivers can translate from interface levels to internal voltage levels. Examples of standard interface levels include Transistor-to-Transistor Logic (TTL) or Complementary Metal Oxide...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H03K3/356H03K19/003H03K5/151H03K5/00
CPCH03K3/356113H03K5/151H03K19/00323H03K2005/00136
Inventor 安基特·斯里瓦斯塔瓦全孝宏
Owner QUALCOMM INC