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4-transistor nonvolatile memory cell with pmos-nmos-pmos-nmos structure

A non-volatile, memory technology, applied in read-only memory, static memory, information storage, etc., can solve the problem of occupying a large area

Active Publication Date: 2015-12-16
NAT SEMICON CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, a 4-transistor all-PMOS NVM cell occupies a relatively large area

Method used

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  • 4-transistor nonvolatile memory cell with pmos-nmos-pmos-nmos structure
  • 4-transistor nonvolatile memory cell with pmos-nmos-pmos-nmos structure
  • 4-transistor nonvolatile memory cell with pmos-nmos-pmos-nmos structure

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Embodiment Construction

[0013] figure 2 An embodiment of a non-volatile memory (NVM) cell structure 200 according to the inventive concept is shown. The NVM cell structure 200 includes a PMOS control transistor P w , NMOS control transistor N c , PMOS erase transistor P e And NMOS read transistor N r , Where the PMOS control transistor P w It has a source electrode, a drain electrode and a body electrode, and a gate connected to the data storage node FG. The NMOS control transistor N c Have a common connection to receive the control voltage V c The source electrode, drain electrode and body electrode and the gate connected to the data storage node FG, the PMOS erase transistor P e Have a common connection to receive the erase voltage V e The source electrode, drain electrode and body electrode and the gate connected to the data storage node FG, the NMOS read transistor N r It has a source electrode, a drain electrode and a body electrode, and a gate connected to the data storage node.

[0014] reference ...

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PUM

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Abstract

A non-volatile memory (NVM) cell structure comprising a PMOS programming transistor, an NMOS control transistor, a PMOS erasing transistor and an NMOS reading transistor, wherein the PMOS programming transistor has a source electrode, a drain electrode and a body electrode and The gate connected to the data storage node; the NMOS control transistor has source, drain and body electrodes commonly connected to receive the control voltage and the gate connected to the data storage node; the PMOS erase transistor has a common connection to receive a source electrode, a drain electrode and a body electrode of an erase voltage and a gate connected to the data storage node; and an NMOS read transistor having a source electrode, a drain electrode and a body electrode and a gate connected to the data storage node .

Description

Technical field [0001] The present invention relates to integrated circuit memory devices, in particular to the following 4-transistor non-volatile memory (NVM) cells, which use PMOS-NMOS-PMOS-NMOS structure to significantly reduce the cell area, and by using reverse Fowler-Nordheim tunnel Through programming provides very small programming current. Background technique [0002] US Patent No. 7,164,606B1 issued by Poplevine et al. on January 16, 2007 discloses an all-PMOS4 transistor non-volatile memory (NVM) cell programmed by reverse Fowler-Nordheim tunneling. US Patent No. 7,164,606 is incorporated herein by reference in its entirety to provide background information about the present invention. [0003] reference figure 1 As disclosed in U.S. Patent No. 7,164,606, according to a method of programming an NVM array including all-PMOS4 transistor NVM cells with a floating gate connected in common, for each cell 100 to be programmed in the array, all of the cell The electrodes ar...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L27/115H01L21/8247G11C16/10
CPCG11C16/0441G11C16/10
Inventor P·珀普立文E·胡H·林(詹姆斯)A·J·富兰克林
Owner NAT SEMICON CORP