Device and method for testing performance degradation caused by transistor lattice deformation
A technology of a testing device and a testing method, applied in the field of microelectronics, can solve the problems of inaccurate calculation of the lattice deformation of the transistor, uneven stress on the transistor, uneven stress on the chip, etc. The effect of overcoming the limited range of mechanical stress and improving the range of mechanical stress
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[0035] Refer to attached figure 1 , a test device for performance degradation caused by transistor lattice deformation, including five parts: 1 is a base, 2 is a precision displacement platform, 3 is a spacer, 4 is a carrier, and 5 is a pressing block. in,
[0036]The cuboid base 1 is located at the bottom of the device, and one end is provided with two rows and two columns of four screw holes, which are connected with the precision displacement platform 2 on it with screws; the other end is provided with four rows and three columns of twelve screw holes. When the invention fixes the spacer 3, it can be connected with the spacer 3 on it with screws through one row of screw holes according to the specific lattice deformation test requirements. In the embodiment of the present invention, the spacer 3 is fixed on a row of screw holes on the side closest to the precise displacement platform 2 with screws.
[0037] The precision displacement platform 2 is located on the upper lef...
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