Universal debugging interface-based SoC (System on Chip) hardware debugger

Abstract

The invention discloses a universal debugging interface-based SoC (System on Chip) hardware debugger, which comprises a universal debugging interface, a TAP controller, a scan chain, a debugging control register module, a synchronizing module, a JTAG-AHB (Joint Test Action Group-Advanced High-performance Bus) protocol conversion module, an AHB-DMA (Advanced High-performance Bus-Direct Memory Access) module, an AHB bus controller, a debug support unit (DSU), an SoC peripheral module and a processor for supporting debugging. According to the universal debugging interface-based SoC hardware debugger, a JTAG port is applied to the DSU of a GAISLER laboratory open source for the first time, the scan chain is prevented from being plugged into a key path of the processor, and the structure and the performance of the SoC hardware debugger are superior to those of the normal hardware debugging modules at present. The SoC hardware debugger has beenis subjected to tape-out verification to prove that the function is correct and reliable.

Description

Technical field: [0001] The invention belongs to the field of semiconductor integrated circuits and relates to a SoC hardware debugger based on a general debugging interface. Background technique: [0002] According to the resources used in the SoC (System on Chip) debugging process, SoC debugging can be divided into software debugging and hardware debugging. Software debugging is mainly to reside in the monitoring program in the running program, and its debugging function is relatively simple, which can no longer meet the actual engineering needs; the strategy of hardware debugging is to integrate related functional modules that support debugging in the SoC system. Operate these functional modules to quickly locate problems in the use of SoC circuits. Hardware debugging has become the mainstream of debugging technology in SoC engineering applications. [0003] A typical hardware-based debug system such as figure 1 Shown in 100. The high-level debugging tool 101 is a wind...

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Problems solved by technology

[0009] Based on the above-mentioned mainstream hardware debugging modules in the industry, it can be known that the ARM debugging system uses the JTAG pin debugging in the SoC circuit for boundary scan and chip interconnection testing in order to unify the chip-level testing and chip-level debugging methods. Although the precious pin resources of the chip are saved, the ARM debugging system inserts the scan chain on the critical path of the processor, which has an "intrusive" impact on the system and limits the improvement and exertion of system performance.

The debugging support module DSU based on the UART serial port uses the serial port to transmit debugging information, and the debugging speed is slow. It needs five additional chip pins including uart_tx, uart_rx, DBGEN, DBGQER, and DBGREQ, but does not need to insert an additional scan connection, and because the 500 The use of 502 makes the debugging system have no "intrusive" influence on the performance of SoC. Its major defect is that the debugging of chip-level SoC can use the debugging support module DSU based on UART serial port, but due to the higher application level (such as Board-level, whole machine) can only be debugged through the IEEE standard JTAG interface, so the debugging support module DSU based on the UART serial port cannot unify the chip machine, board-level test and chip-level test methods. Different test versions are produced during the debugging phase, which greatly wastes resources

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