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Fast computation of products by dyadic fractions with sign-symmetric rounding errors

A symbol-vector technique, applied in the field of fast calculation of the product of the union-vector fraction and the symbol-symmetric rounding error, and can solve problems such as increasing the rounding error

Active Publication Date: 2013-03-20
QUALCOMM INC
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Problems solved by technology

Since right shifting is a non-linear operation, arithmetic right shifting can increase rounding errors and produce results that may not be equal to the result of multiplication after the right shift

Method used

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  • Fast computation of products by dyadic fractions with sign-symmetric rounding errors
  • Fast computation of products by dyadic fractions with sign-symmetric rounding errors
  • Fast computation of products by dyadic fractions with sign-symmetric rounding errors

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Embodiment Construction

[0014] Discrete Cosine Transform (DCT) and Inverse Discrete Cosine Transform (IDCT) perform multiplication operations with respect to irrational constants (ie, cosine). In the design of an implementation of the DCT / IDCT, the approximation of the computed product of these irrational constants can be performed using fixed-point arithmetic. One technique for converting floating-point values ​​to fixed-point values ​​is based on finding the irrational factor α by merging vector fractions i approximation:

[0015] alpha i ≈a i / 2 k (1)

[0016] where a i and k are both integers. x and factor α i The multiplication of provides an approximate implementation in integer arithmetic, as follows:

[0017] xα i ≈(x*a i )>>k (2)

[0018] Where >> indicates a bitwise right shift operation.

[0019] The number k of exact bits can affect the complexity of the union-vector rational approximation. In a software implementation, the exact parameter k may be constrained by the widt...

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Abstract

The application relates to fast computation of products by dyadic fractions with sign-symmetric rounding errors. A product of an integer value and an irrational value may be determined by a sign-symmetric algorithm. A process may determine possible algorithms that minimize metrics such as mean asymmetry, mean error, variance of error, and magnitude of error. Given an integer variable x and rational dyadic constants that approximate the irrational fraction, a series of intermediate values may be produced that are sign-symmetric. The intermediate values may include a sequence of addition, subtraction and right shift operations the when summed together approximate the product of the integer and irrational value. Other operations, such as additions or subtractions of 0s or shifts by 0 bits may be removed.

Description

[0001] Information about divisional applications [0002] This application is a divisional application. The parent case of this divisional case is an invention patent application with an application date of August 28, 2008, an application number of 200880104677.2, and an invention title of "Quick calculation of the product of a parallel vector fraction and a symbolic symmetric rounding error". technical field [0003] The subject matter herein relates generally to processing, and in particular to approximation techniques for use in hardware and software processing. Background technique [0004] Arithmetic shifts can be used to perform signed integer multiplication or division by powers of 2. Shifting a signed or unsigned binary number to the left by n bits has the effect of multiplying it by 2n. Right shifting a 2's complement signed binary number by n bits has the effect of dividing it by 2n, but it usually rounds (ie, towards negative infinity). Since right shifting is...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F17/14G06F7/533H04N7/26H04N7/30
CPCG06F7/533H04N7/26702H04N7/30H04N19/00775G06F7/49942G06F17/147H04N19/00478H04N19/42H04N19/60G06F7/483
Inventor 尤里娅·列兹尼克
Owner QUALCOMM INC
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