NAND flash-based threshold voltage check method and apparatus, and NAND storage device

A threshold voltage, storage device technology, applied in the field of memory, can solve problems affecting the accuracy of data word line data reading and writing, etc.

Inactive Publication Date: 2017-07-21
GIGADEVICE SEMICON (BEIJING) INC
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0005] Embodiments of the present invention provide a threshold voltage verification method, device, and NAND storage device based on NAND flash memory to solve the problem in the prior art that the memo

Method used

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  • NAND flash-based threshold voltage check method and apparatus, and NAND storage device
  • NAND flash-based threshold voltage check method and apparatus, and NAND storage device
  • NAND flash-based threshold voltage check method and apparatus, and NAND storage device

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Embodiment 1

[0039] figure 2 It is a flow chart of the threshold voltage verification method based on NAND flash memory in Embodiment 1 of the present invention. This embodiment is applicable to the situation of threshold voltage drift of memory cells based on NAND flash memory and is applied to NAND storage devices. The method can be based on The threshold voltage verification device of NAND flash memory is implemented, and the device can be realized by software and / or hardware, and can be integrated in the NAND storage device.

[0040] Wherein, the storage device includes a plurality of word lines and a plurality of NAND memory cells, and each word line is respectively connected to a corresponding memory cell, and the word lines include a dummy word line and a data word line, and each group of data word lines is connected to each corresponding to the set of dummy word lines. Such as figure 2 As shown, the threshold voltage verification method based on NAND flash memory includes:

[00...

Embodiment 2

[0047] image 3 It is a flow chart of the threshold voltage verification method based on NAND flash memory provided by Embodiment 2 of the present invention. In this embodiment, on the basis of the foregoing embodiments, the threshold voltage verification method based on NAND flash memory is optimized.

[0048] Such as image 3 As shown, the threshold voltage verification method based on NAND flash memory includes:

[0049] S310. When performing an erasing operation on the selected memory cell, add the erase voltage on the data word line corresponding to the selected memory cell to the dummy word line corresponding to the data word line, so that the dummy word line The memory cell corresponding to the line performs an erase operation.

[0050] S320. Apply a verification voltage to the dummy word line to which the erasing voltage is applied, and verify whether the threshold voltage of the memory cell corresponding to the dummy word line reaches a preset range, wherein the ve...

Embodiment 3

[0061] Figure 4 It is a schematic structural diagram of a threshold voltage verification device based on NAND flash memory in Embodiment 3 of the present invention. The device is applied to a NAND storage device, and the storage device includes a plurality of word lines and a plurality of NAND memory cells, and each word line is respectively connected with corresponding memory cells, wherein the word lines include dummy word lines and data word lines, and each group of data word lines corresponds to each group of dummy word lines, such as Figure 4 As shown, the device specifically includes:

[0062] The erasing voltage applying module 410 is used to apply the erasing voltage on the data word line corresponding to the selected memory cell to the dummy word line corresponding to the data word line when performing an erasing operation on the selected memory cell to perform an erase operation on the memory cells corresponding to the dummy word line.

[0063] In the embodiment ...

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Abstract

Embodiments of the invention disclose an NAND flash-based threshold voltage check method and apparatus, and an NAND storage device. The method is applied to the NAND storage device. The storage device comprises a plurality of word lines and a plurality of NAND memory units; each word line is connected with the corresponding memory unit; the word lines include virtual word lines and data word lines; and each group of the data word lines corresponds to each group of the virtual word lines. The method comprises the steps of loading an erasure voltage on the data word line, corresponding to the selected memory unit, to the virtual word line corresponding to the data word line when the selected storage unit is subjected to erasure operation, thereby executing the erasure operation on the memory unit corresponding to the virtual word line. According to the method and the apparatus, the influence on data reading/writing accuracy of the memory unit corresponding to the data word line due to right shift of a threshold voltage of the memory unit corresponding to the virtual word line can be prevented; and the threshold voltage of the memory unit corresponding to the virtual word line is adjusted to be in a normal range.

Description

technical field [0001] Embodiments of the present invention relate to memory technology, and in particular to a threshold voltage verification method and device based on NAND flash memory, and a NAND storage device. Background technique [0002] NAND flash memory is a kind of Flash memory, which belongs to non-volatile semiconductor memory. NAND flash memory includes many data blocks, and each data block is composed of many memory cells for reading and writing data. These memory cells are arranged in an array. A specific memory cell in the array is usually selected through a word-line (WL) and a pair of bit-lines (Bit-line, BL). The word line is usually coupled to each memory cell in a row. One or more control gates of the cell, a bit line pair (BL pair), typically couple the storage point of each memory cell within a column to a sense amplifier. By controlling the high and low voltages of the word line and the bit line, the reading, writing and erasing operations of the m...

Claims

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Application Information

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IPC IPC(8): G11C29/50G11C29/12G11C16/10G11C16/08G11C11/34
CPCG11C29/50004G11C11/34G11C16/08G11C16/105G11C29/12G11C2029/1202
Inventor 苏志强刘会娟李建新
Owner GIGADEVICE SEMICON (BEIJING) INC
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