Method for forming non-planar transistor

Abstract

The invention provides a method for forming a non-planar transistor. The method includes: firstly, providing a substrate defining an active region and a peripheral region, with a plurality of ultra-shallow channel isolators connected to the active region of the substrate; secondly, removing the ultra-shallow channel isolators to expose part of a sidewall of the substrate; forming a conductive layer on the active region and the peripheral region on the substrate to cover the part of the sidewall of the substrate; patterning the conductive layer to allow the conductive layer to form a gate of a planar transistor in the peripheral region and form a gate of at least one non-planar transistor in the active region; and forming a source and a drain on two sides of the gate of each non-planar transistor.

Description

technical field [0001] The invention relates to a method for making a non-planar transistor structure, in particular to a method capable of simultaneously forming a non-planar transistor and a planar transistor. Background technique [0002] In recent years, with the continuous miniaturization of various consumer electronic products, the design size of semiconductor components has also been continuously reduced to meet the trend and product requirements of high integration, high efficiency and low power consumption. [0003] However, with the miniaturization of electronic products, the existing planar transistors cannot meet the requirements of the products. Therefore, a non-planar fin transistor (Fin-FET) technology has been developed, which has a three-dimensional gate channel (channel) structure, which can effectively reduce the leakage of the substrate and reduce the short channel. effect, and has a higher drive current. However, since the fin transistor is a three-dim...

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Problems solved by technology

However, since the fin transistor is a three-dimensional structure, it is more complicated than the traditional structure, and the manufacturing difficulty is relatively high. Generally, it is usually formed on a silicon-on-insulator (SOI) substrate. If it is to be compatible with the existing silicon The base process has a certain degree of difficulty

Moreover, due to the special manufacturing method of fin transistors, certain problems will also be encountered when integrating with existing planar transistors.

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