Methods of forming non-planar transistors

Abstract

The present invention provides a method of forming a non-planar transistor. First, a substrate is provided, on which an active area and a peripheral area are defined. A plurality of ultra-shallow trench isolations are formed in the active region bonded to the substrate. Portions of each ultra-shallow trench isolation are then removed to expose portions of sidewalls of the substrate. A conductive layer is formed on the active area and the peripheral area on the base, and covers part of the sidewall of the base. The conductive layer is patterned such that the conductive layer forms gates of planar transistors in the peripheral region and at least one gate of non-planar transistors in the active region. Source / drain are formed on both sides of the gate of the non-planar transistor.

Description

technical field [0001] The invention relates to a method for making a non-planar transistor structure, in particular to a method capable of simultaneously forming a non-planar transistor and a planar transistor. Background technique [0002] In recent years, with the continuous miniaturization of various consumer electronic products, the design size of semiconductor components has also been continuously reduced to meet the trend and product requirements of high integration, high efficiency and low power consumption. [0003] However, with the miniaturization of electronic products, the existing planar transistors cannot meet the requirements of the products. Therefore, a non-planar fin transistor (Fin-FET) technology has been developed, which has a three-dimensional gate channel (channel) structure, which can effectively reduce the leakage of the substrate and reduce the short channel. effect, and has a higher drive current. However, since the fin transistor is a three-dim...

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Problems solved by technology

However, since the fin transistor is a three-dimensional structure, it is more complicated than the traditional structure, and the manufacturing difficulty is relatively high. Generally, it is usually formed on a silicon-on-insulator (SOI) substrate. If it is to be compatible with the existing silicon The base process has a certain degree of difficulty

Moreover, due to the special manufacturing method of fin transistors, certain problems will also be encountered when integrating with existing planar transistors.

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