Arbitration control method of high-speed data flow in ccd signal processing circuit

Abstract

The invention relates to the technical field of control of signal processing circuit data flow, in particular to an arbitration control method of CCD (Charge Coupled Device) signal processing circuit high speed data flow. The arbitration control method comprises an algorithm module, a read address FIFO (First In First Out) buffer module, a read data FIFO buffer module, a write address FIFO buffer module, a write data FIFO buffer module, a DDR2 (Double Data Rate 2) arbitration controller and a DDR2 controller, wherein the algorithm module makes a write requirement and a read requirement; the read address FIFO buffer module, the read data FIFO buffer module, the write address FIFO buffer module and the write data FIFO buffer module respectively cache addresses and data to be written and read; the DDR2 arbitration controller judges and sequence various applications of DDR2, and arranges the algorithm to control DDR2 memories. According to the invention, the number of external memories can be decreased greatly, resources and PCB space are saved, and DDR2 use efficiency is improved.

Description

technical field [0001] The invention relates to the technical field of a data flow control method for a signal processing circuit, in particular to a high-speed data flow arbitration control method for a CCD signal processing circuit. Background technique [0002] In a CCD camera, in order to meet the needs of the algorithm, it is often necessary to connect some memories around the FPGA as an algorithm data cache. The usual method is to connect a corresponding number of memories for the FPGA according to the number of algorithms that need to cache data in the periphery. In this method, the algorithm directly operates the peripheral memory, and performs data read and write operations on the peripheral memory. [0003] In the early CCD imaging technology, static memory (SRAM) is generally used as the buffer, which can meet the system requirements when the frame rate of the CCD camera is not high and the number of pixels is small, but with the popularization of 1080p data forma...

AI Technical Summary

Problems solved by technology

[0003] In the early CCD imaging technology, static memory (SRAM) is generally used as the buffer, which can meet the system requirements when the frame rate of the CCD camera is not high and the number of pixels is small, but with the popularization of 1080p data format And when the high frame rate ratio is 30 frames or even higher frame rate video stream, the speed and capacity of the static memory can no longer meet the system requirements. The main defects are mainly manifested in: 1: When there are many algorithms to run, you need to use more Memory, which greatly increases the area of ​​the PCB layout and increases the cost; 2: The data capacity of the static memory generally does not exceed 16M bits, and it is no longer possible to store the image of 2M pixels (32M bits) in the next frame of 1080p video format; 3: Static The operating speed of the memory generally does not exceed 100MHz, which cannot satisfy the buffering of 30 frames of 1080p data. Therefore, it is urgent to use a memory with a higher speed and a larger capacity, and to reduce the number of memories as much as possible under the premise of meeting the large-capacity and high-speed transmission. Reduce PCB layout area

[0004] Therefore, although the existing data structure adopts high-speed and large-capacity memory such as DDR2, it directly operates the memory through the algorithm module.

In this way, a DDR2 needs to be assigned to each algorithm module. DDR2 can complete data read and write operations in a short period of time, and enter the idle state for the rest of the time, or run DDR2 in a situation where the data read and write speed is slow. In both cases, DDR2 resources are greatly wasted

Images