HPI (Host Port Interface) bus upper computer interface based on FPGA (Field Programmable Gate Array)

Abstract

The invention belongs to the field of a bus interface and specifically relates to an HPI (Host Port Interface) bus upper computer interface based on an FPGA (Field Programmable Gate Array). The invention aims to use an FPGA structure to realize an HPI interface of a DSP (Digital Signal Processor) of the whole series of TMS320C6000 compatible with TI. The HPI bus upper computer interface based on the FPGA comprises a bottom layer, a middle layer and a top layer, wherein the bottom layer has the functions of generating HPI interface control signals: HCNTL [1:0], HHWIL and HRW, and controlling a read-write accessing timing sequence of an HPI register; the middle layer has the function of realizing a basic HPI interface accessing flow; and the top layer has the function of generating a control logic and controlling the skipping of the flow in the middle layer so as to realize a complex data transmission function. The HPI bus upper computer interface based on the FPGA has the advantages: the HPI interface of the DSP of the whole series of TMS320C6000 compatible with TI is realized by the bottom layer and the middle layer of the HPI bus upper computer interface; the interface has generality; the top layer is cross-linked with the middle layer through DSP standard HPI interface signals HINT and DSPINT and is free from signal coupling with the bottom layer; the top layer can be customized for different applications according to tasks or applications; the middle layer is only adaptively modified; the bottom layer is completely free from modification; and the flexibility is ultrahigh.

Description

technical field [0001] The invention belongs to the field of bus interface, and relates to the FPGA realization of the interface of the HPI bus upper computer of the TMS320C64X series DSP of TI. Background technique [0002] Radar pulse signal sorting technology is the core issue of current electronic warfare, and it is also an area of ​​defense technology that our country has paid more attention to in recent years. Among them, the TMS320C6000 series DSP is used, and the HPI (host port interface) bus is a parallel interface configured by TI's TMS320C6000 series DSP. At present, it is necessary to solve the problem of using FPGA to realize the bus for the communication between FPGA and this series of DSP. [0003] Introduction to HPI bus [0004] 1.1 Introduction [0005] HPI (host port interface) bus is a parallel interface configured by TI's TMS320C6000 series DSP. The upper computer (host) masters the master control of the interface, through the control of the HPI cont...

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