K nearest neighbor classifier based on field programmable gate array (FPGA)
A K-nearest neighbor and classifier technology, applied in the directions of instruments, processor architecture/configuration, character and pattern recognition, etc., can solve the problems of slow calculation speed, large amount of calculation, difficult to achieve real-time processing, etc., to achieve the effect of speeding up
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[0035] refer to figure 1, the present invention includes: N+1 read-only storage units 1, serial-in-parallel-out unit 2, distance calculation unit 3, tag delay unit 4, K-nearest neighbor selection unit 5 and decision unit 6. in:
[0036] The N+1 read-only memory units 1, the first N read-only memory units ROM(1), ROM(2), ... ROM(N) are respectively used to store N-dimensional feature data of training samples, N=7; Its last read-only memory unit ROM (N+1) is used for storing the category label of training sample;
[0037] The serial-in parallel-out unit 2 is provided with an input port and N output ports, and its input port is used as the input port of the entire K-nearest neighbor classifier for serially inputting N feature data of samples to be tested Convert to parallel N-dimensional feature data. The structure of the serial-in-parallel-out unit is as follows figure 2 shown.
[0038] The distance calculation unit 3 is provided with N pairs of input ports and 1 output po...
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