Substrate, semiconductor package and fabrication method thereof

Abstract

The invention relates to a substrate, a semiconductor package, and a fabrication method thereof. The semiconductor package includes: a dielectric layer with a plurality of holes on the surface, a patterned line layer encased in the dielectric layer and exposing the holes, a plurality of first re-routed line layers formed on the dielectric layer and connected with the patterned line layer in the first hole, wherein the first re-routed line layers comprise a plurality of first connection pads, chips formed on the dielectric layer and electrically connected with the first connection pads, and an encapsulated colloid for partly covering the first re-routed line layers. By the design of the first re-routed line layers, the patterned line does not need to cooperate with the number of the connection pads electrically connected with the chip, thus the flexibility of circuit design is improved.

Description

technical field [0001] The invention relates to a semiconductor package, in particular to a thin semiconductor package and its manufacturing method. Background technique [0002] There are many types and types of traditional semiconductor packages that use lead frames as chip carriers. For example, the external leads in the existing quad flat package (QFP) semiconductor packages are used to When the pin spacing is less than 0.65mm, the outer lead pin is easy to bend. Therefore, in order to solve the problem of deformation of the external leads, a new quad flat non-leaded (QFN) package structure has been newly developed, so that the size of the semiconductor package can be reduced. [0003] see Figure 1A , which is the QFN semiconductor package 1 disclosed in U.S. Patent No. 6,281,568. It mainly arranges the chip 14 on the lead frame 11 and electrically connects the chip 14 and the upper side of the lead pin 112 through the bonding wire 15, and also performs the package mol...

AI Technical Summary

Problems solved by technology

[0006] However, in the existing QFN semiconductor package 1', because the circuit 111 is used as a guide pin, and the position of the bonding pad 111a is defined by the opening 100, the design flexibility of the circuit 111 is limited, and it is impossible to Design the layout of the line 111 at will

[0007] In addition, when the chip is developed to have a larger number or higher density of electrical connection pads, a highly integrated (Highly Integrated) chip is intended to be used. Due to the limited area of ​​the circuit 111, it is impossible to form enough openings 100. As a result, it cannot meet the needs of highly integrated chips, resulting in the inability to make semiconductor packages meet the needs of high pin count and high-density circuits.

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