Processing method and processing system for write enable signals in storage of DMA (direct memory access) downlink data
A downlink data and write enable technology, applied in the direction of electrical digital data processing, instruments, etc., can solve the problems of increasing circuit complexity and production cost
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Embodiment 1
[0057] image 3 It shows the flow chart of the processing method of the write enable signal when saving the DMA downlink data provided by the first embodiment of the present invention. In this embodiment, after determining the auxiliary signal, the response delay signal and the first mark of the downloaded data, according to the above Determine the 3 signals to determine the write enable signal. The details are as follows:
[0058] In step S31, the auxiliary signal is determined according to the signal of the total number of bytes to be transferred by the direct storage access DMA and the signal of the DMA transfer start address.
[0059] In this embodiment, X[m:n] is used to represent the value composed of the nth bit to the mth bit of the variable X.
[0060] Among them, the steps of determining the auxiliary signal according to the total number of bytes to be transmitted by the direct storage access DMA and the DMA transmission start address signal are as follows:
[006...
Embodiment 2
[0092] In order to illustrate the determination process of the write enable signal more clearly, several application examples are used for illustration below. In this embodiment, assuming that the number of bits of the DMA read-in data dma_ddata is 32 bits, and the write enable signal WEN is active high, then:
[0093] 1. Assume that dma_cnt[15:0] is the value composed of the 0th bit to the 15th bit of the total number of bytes signal to be transmitted by DMA, and dma_addr[1:0] indicates the low 2 of the DMA transmission start address signal The value composed of bits, if dma_cnt[15:0]+dma_addr[1:0]≤4, or dma_addr[1:0]=0, then WEN is equal to the data download control signal dma_dwr, when dma_dwr is valid, WEN is valid , when dma_dwr is invalid, WEN is invalid, specifically as Figure 4 shown.
[0094] 2. If dma_cnt[15:0]+dma_addr[1:0]>4, dma_addr[1:0] is not equal to 0 and the auxiliary signal nee_ack_done is low, then when dma_dwr is high for the first time, WEN is invalid...
Embodiment 3
[0097] Figure 7 The structure of the system for processing the write enable signal when storing DMA downlink data provided by the third embodiment of the present invention is shown. For the convenience of description, only the parts related to the embodiment of the present invention are shown.
[0098] The processing system for writing enable signals when saving DMA downlink data can be used for various information processing terminals connected to servers through wired or wireless networks, such as handheld computers, computers, notebook computers, personal digital assistants (Personal Digital Assistant, PDA), etc. , can be a software unit, a hardware unit, or a combination of software and hardware running in these terminals, or can be integrated into these terminals as an independent pendant or run in the application systems of these terminals, where:
[0099] The auxiliary signal determining unit 71 is configured to determine the auxiliary signal according to the signal of...
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