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Processing method and processing system for write enable signals in storage of DMA (direct memory access) downlink data

A downlink data and write enable technology, applied in the direction of electrical digital data processing, instruments, etc., can solve the problems of increasing circuit complexity and production cost

Active Publication Date: 2013-04-10
ANYKA (GUANGZHOU) MICROELECTRONICS TECH CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0024] The embodiment of the present invention provides a method for processing the write enable signal when saving DMA downlink data, aiming at solving the problem that the existing method for determining the write enable signal needs to use additional registers to save the number of written data, thereby increasing the circuit Issues of complexity and production cost

Method used

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  • Processing method and processing system for write enable signals in storage of DMA (direct memory access) downlink data
  • Processing method and processing system for write enable signals in storage of DMA (direct memory access) downlink data
  • Processing method and processing system for write enable signals in storage of DMA (direct memory access) downlink data

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Embodiment 1

[0057] image 3 It shows the flow chart of the processing method of the write enable signal when saving the DMA downlink data provided by the first embodiment of the present invention. In this embodiment, after determining the auxiliary signal, the response delay signal and the first mark of the downloaded data, according to the above Determine the 3 signals to determine the write enable signal. The details are as follows:

[0058] In step S31, the auxiliary signal is determined according to the signal of the total number of bytes to be transferred by the direct storage access DMA and the signal of the DMA transfer start address.

[0059] In this embodiment, X[m:n] is used to represent the value composed of the nth bit to the mth bit of the variable X.

[0060] Among them, the steps of determining the auxiliary signal according to the total number of bytes to be transmitted by the direct storage access DMA and the DMA transmission start address signal are as follows:

[006...

Embodiment 2

[0092] In order to illustrate the determination process of the write enable signal more clearly, several application examples are used for illustration below. In this embodiment, assuming that the number of bits of the DMA read-in data dma_ddata is 32 bits, and the write enable signal WEN is active high, then:

[0093] 1. Assume that dma_cnt[15:0] is the value composed of the 0th bit to the 15th bit of the total number of bytes signal to be transmitted by DMA, and dma_addr[1:0] indicates the low 2 of the DMA transmission start address signal The value composed of bits, if dma_cnt[15:0]+dma_addr[1:0]≤4, or dma_addr[1:0]=0, then WEN is equal to the data download control signal dma_dwr, when dma_dwr is valid, WEN is valid , when dma_dwr is invalid, WEN is invalid, specifically as Figure 4 shown.

[0094] 2. If dma_cnt[15:0]+dma_addr[1:0]>4, dma_addr[1:0] is not equal to 0 and the auxiliary signal nee_ack_done is low, then when dma_dwr is high for the first time, WEN is invalid...

Embodiment 3

[0097] Figure 7 The structure of the system for processing the write enable signal when storing DMA downlink data provided by the third embodiment of the present invention is shown. For the convenience of description, only the parts related to the embodiment of the present invention are shown.

[0098] The processing system for writing enable signals when saving DMA downlink data can be used for various information processing terminals connected to servers through wired or wireless networks, such as handheld computers, computers, notebook computers, personal digital assistants (Personal Digital Assistant, PDA), etc. , can be a software unit, a hardware unit, or a combination of software and hardware running in these terminals, or can be integrated into these terminals as an independent pendant or run in the application systems of these terminals, where:

[0099] The auxiliary signal determining unit 71 is configured to determine the auxiliary signal according to the signal of...

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Abstract

The invention is applicable to the field of multimedia data processing, and provides a processing method and a processing system for write enable signals in the storage of DMA (direct memory access) downlink data. The method includes the following steps: determining an auxiliary signal according to a total byte number signal and an initial DMA transmission address signal to be transmitted in DMA; determining a response delay signal according to a clock signal and a DMA request response signal; determining a first downloaded data marker according to a clock signal, a DMA request signal and a data download control signal; and determining a write enable signal according to the data download control signal, the auxiliary signal, the response delay signal and the first downloaded data marker. Since the write enable signal can be determined as long as the auxiliary signal, the response delay signal and the first downloaded data marker are determined, the embodiment of the invention decreases the circuit complexity, and reduces the production cost.

Description

technical field [0001] The invention belongs to the field of multimedia data processing, and in particular relates to a processing method and system for writing enable signals when storing DMA downlink data. Background technique [0002] Direct memory access (DMA) interface: [0003] 1.dma_req: 1 bit in dma_req, DMA request signal, active high. The direct storage access control unit pulls dma_req high when the clock triggers an edge moment and requests DMA data transmission, and when the clock triggers an edge moment dma_ack is high, the direct storage access control unit pulls dma_req low. [0004] 2. dma_addr: dma_addr has a total of 32 bits, the DMA transmits the start address signal, and the direct storage access control unit sends out the dma_addr signal while pulling the dma_red signal high. [0005] 3. dma_cnt: dma_cnt has a total of 16 bits, the total number of bytes to be transferred in this DMA transfer, and the direct storage access control unit sends out the dm...

Claims

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Application Information

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IPC IPC(8): G06F13/28
Inventor 冷永春胡胜发
Owner ANYKA (GUANGZHOU) MICROELECTRONICS TECH CO LTD