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Low-voltage operation storage unit circuit of SRAM (Static Random Access Memory)

A storage unit circuit, low-voltage technology, applied in the direction of information storage, static memory, digital memory information, etc., to achieve the effect of reducing power consumption

Inactive Publication Date: 2013-05-01
SOUTHEAST UNIV
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

Although certain design requirements can be met by adjusting the size of the device, it has become unrealistic to achieve the design goal simply by adjusting the size of the device, and the design of the memory cell structure has also become the key

Method used

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  • Low-voltage operation storage unit circuit of SRAM (Static Random Access Memory)
  • Low-voltage operation storage unit circuit of SRAM (Static Random Access Memory)
  • Low-voltage operation storage unit circuit of SRAM (Static Random Access Memory)

Examples

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Embodiment Construction

[0016] see figure 1 , The SRAM storage unit circuit with simple structure and low voltage operation of the present invention includes 2 PMOS transistors MP1, MP2 and 6 NMOS transistors MN1-MN6, and the circuit also includes 2 control ports cont and Colum.

[0017] The source end of the MP1 tube is connected to the power supply voltage VDD, and its drain end is connected to the source end of the MN5 tube, the drain end of the MN3 tube, the gate end of the MP2 tube, and the gate end of the MN2 tube, and the gate end is connected to the gate end of the MN1 tube, MN2 tube The drain end of the tube, the drain end of MP2 and the source end of the MN6 tube;

[0018] The source end of the MP2 tube is connected to the power supply voltage VDD;

[0019] The source terminal of the MN1 tube is connected to the ground voltage VSS, and its drain terminal is connected to the source terminal of the MN3 tube; the source terminal of the MN2 tube is connected to VSS; the gate terminal of the MN...

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Abstract

The invention discloses a low-voltage operation storage unit circuit of an SRAM (Static Random Access Memory), employing a dual-port structure with one reading-writing port, and comprising 2 PMOS (P-channel Metal Oxide Semiconductor) tubes MP1 and MP2, 6 NMOS (N-channel Metal Oxide Semiconductor) tubes MN1-MN6, and two control ports cont and Colum. In the case of ensuring right reading and writing, the storage unit circuit provided by the invention can work at low voltage near a sub-threshold, so that the power consumption is reduced; compared with a conventional storage unit circuit with one reading-writing port, the 8T storage unit circuit of the invention can employ a CMUX structure, and therefore the power consumption of the whole SRAM is reduced.

Description

technical field [0001] The invention belongs to the technical field of integrated circuits, relates to the technology of reducing unit power consumption, and is a storage unit circuit of SRAM with low voltage operation. Background technique [0002] At present, from electronic products to Internet shared servers, and network equipment, controlling power consumption has become the main limitation of adding functions, and power supply voltage is an important factor determining power consumption, and the biggest obstacle to the reduction of power supply voltage is embedded SRAM The minimum operating voltage of the module. [0003] The memory cell array circuit is an important part of SRAM, and it is often the bottleneck of power consumption in system design. The continuous improvement of the market's demand for various portable devices also puts forward higher requirements for the power consumption reduction technology of memory cell arrays. . In the new generation of integra...

Claims

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Application Information

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IPC IPC(8): G11C11/413
Inventor 刘波柏娜常红
Owner SOUTHEAST UNIV
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