Layout Structure of Isolated High Voltage Field Effect Transistor

Abstract

The invention discloses an isolation type high voltage resistance field effect transistor (FET). A drift area of a drain region on a silicon substrate is extended to cover a whole source region, the isolation of a substrate of the source region and the silicon substrate is realized, and therefore the effects that the substrate electric potential of the FET cannot be affected by the electric potential of the silicon substrate, and the electric potential can be added independently can be achieved. The invention further provides a layout structure of the isolation type high voltage resistance FET. The layout structure of the isolation type high voltage resistance FET comprises the drain region, the source region, the drain region drift area, a drift region, a source region poly silicon field plate, grid electrodes and a drain region poly silicon field plate, wherein the source region poly silicon field plate, the grid electrodes and the drain region poly silicon field plate are all in U-shaped enclosed structures, and the drain region poly silicon field plate is located inside the source region poly silicon field plate and the grid electrodes. Due to the structure that the source region completely surrounds the drain region, and meanwhile, the substrate, drift region implantation and a doped region are adopted at a circular arc position at the bottom of a U-shaped inner layer to form an isolation voltage resistance ring, the situation that high voltage electric potential is located outside the position, and low voltage electric potential is located inside the position is avoided, breakdown voltage can be affected in a concentrative mode by a power line, and therefore the high voltage resistant capacity is achieved, and the area of a device is reduced at the same time.

Description

technical field [0001] The invention relates to the field of semiconductor integrated circuits, in particular to an isolated high withstand voltage field effect transistor and a layout structure. Background technique [0002] The currently used high withstand voltage field effect transistor is usually a non-isolated high withstand voltage N-type field effect transistor formed on a P-type silicon substrate substrate 301, with a cross section as figure 2 As shown, the P-type silicon substrate substrate 301 is implanted with N-type implantation to form an N-type drift region 302, and the source region is located outside the N-type drift region 302, so that the substrate P-type well 303 of the field effect transistor and the P-type silicon substrate substrate 301 together. The drain drift region 403 is led out by the N+ active region 307 to form the drain region 401. A field oxygen isolation 305 is formed in the drain drift region 403, and an ion implantation type different fro...

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Problems solved by technology

[0004] The substrate of the above-mentioned non-isolated high-voltage field-effect transistor cannot be isolated from the silicon substrate substrate. In some circuit designs, it cannot be used when the source region is required to be connected to a certain potential, and the above-mentioned structure cannot be realized.

In terms of improving the withstand voltage, in the existing non-isolated high withstand voltage field effect transistor structure, figure 1 The A-A cross-section of the drain drift region position is shown using image 3 The shown structure, that is, the P-type silicon substrate substrate 301 and the N-type drift region 302 carry out withstand voltage, because the PN junction is completely depleted to withstand high voltage, in order to provide enough depletion regions to withstand sufficient withstand voltage, The required P-type substrate area is relatively large, which will cause the area of ​​the entire device to be too large

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