A Differential Input Successive Approximation Analog-to-Digital Conversion Method

Abstract

The invention discloses a differential input successive approximation type analog-digital converter. A switched-capacitor network comprises capacitor pairs of which the quantity is identical with that of output binary code digits; a compensation capacitor in a traditional SAR (Successive Approximation) type ADC (Analog to Digital Converter) switched-capacitor network is omitted by brand-new time sequence arrangement of the switch, so that the capacitance at highest order is reduced by 50 percent and the whole total capacitor is also reduced by 50 percent. Charge / discharge current is correspondingly reduced along with the reduction of the capacitance, and thus the integral power consumption is reduced. Meanwhile, the area of a chip is reduced and economic benefits are increased. In the converting process, common-mode voltage variable quantity at the input end of a comparator is compared with that of a traditional structure, N is a digit of the ADC and Vref is equal to the difference of VH and VL.

Description

technical field [0001] The invention relates to a differential input successive approximation analog-to-digital conversion method, which belongs to the field of analog-to-digital converters. Background technique [0002] The successive approximation analog-to-digital converter is an analog-to-digital converter structure with medium and high precision, medium speed and ultra-low power consumption. For applications such as wireless sensor networks and portable devices, analog-to-digital converters are required to operate at low supply voltages. However, as the power supply voltage decreases, the gain of the circuit is limited, and the structure of the successive approximation analog-to-digital converter only includes a comparator, a digital-to-analog converter and a successive approximation register, and does not need a circuit that provides gain. The power consumption of digital circuits will continue to decrease with the scaling-down of the process size, while the power con...

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Problems solved by technology

However, as the power supply voltage decreases, the gain of the circuit is limited, and the structure of the successive approximation analog-to-digital converter only includes a comparator, a digital-to-analog converter, and a successive approximation register, and does not require a gain-providing circuit.

The power consumption of digital circuits will continue to decrease with the process size reduction (scaling-down), while the power consumption of analog circuits is difficult to reduce synchronously with the progress of the process

In the case of capacitive successive approximation ADC with high resolution, a large capacitor is required, which not only consumes a lot of charge and discharge power, but also wastes chip area by making a large capacitor, and the economic benefit is not high.

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