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How to form a pmos transistor

A transistor and gas technology, applied in the field of semiconductor manufacturing, can solve the problems of reducing the performance of PMOS transistors, affecting the stress of the silicon germanium layer, and difficult to control the concentration of germanium, and achieving the effects of increasing the concentration, increasing the stress, and improving the performance.

Active Publication Date: 2016-01-06
SEMICON MFG INT (SHANGHAI) CORP
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  • Application Information

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Problems solved by technology

[0009] In the existing method of forming a silicon germanium layer in the source and drain regions of a PMOS transistor, the concentration of germanium in the silicon germanium layer is relatively low, and the concentration of germanium in the silicon germanium layer is not easy to control, which affects the stress applied to the channel region by the silicon germanium layer. degrades the performance of the PMOS transistor

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  • How to form a pmos transistor
  • How to form a pmos transistor
  • How to form a pmos transistor

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Embodiment Construction

[0050] A silicon germanium layer (SiGe) is formed in the source and drain regions of the PMOS transistor, and the compressive stress formed by lattice mismatch between silicon and silicon germanium is introduced to improve the mobility of carriers in the channel region. Usually, the silicon germanium layer The higher the concentration of germanium in the medium, the greater the compressive stress applied by the silicon germanium layer (SiGe), the faster the mobility of carriers in the channel region, and the more the performance of the PMOS transistor is improved. The inventor found in the existing process of making PMOS transistors with silicon-germanium source and drain regions that the existing method of increasing the concentration of germanium in the silicon-germanium layer is to change the flow ratio of germanium source gas and silicon source gas, but this method improves The concentration of germanium in the silicon germanium layer is limited, generally 20% to 30%, and t...

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Abstract

A forming method of a transistor of a P-channel metal oxide semiconductor (PMOS) comprises the steps: providing a semiconductor substrate, wherein a grid structure is formed on the semiconductor substrate; forming grooves in the semiconductor substrate on both sides of the grid structure; forming at least one silicon-germanium layer in each groove, wherein the surface of each silicon-germanium layer is lower than the surface of the semiconductor substrate or is aligned with the surface of the semiconductor substrate; conducting oxidation treatment on each silicon-germanium layer, forming an oxide layer on the surface of each silicon-germanium layer to consume silicon in each silicon-germanium layer; and removing the oxide layer on the surface of each silicon-germanium layer. The forming method of the transistor of the PMOS can improve concentration of germanium in the silicon-germanium layers and improve the performance of components.

Description

technical field [0001] The invention relates to the field of semiconductor manufacturing, in particular to a method for forming a PMOS transistor. Background technique [0002] With the rapid development of semiconductor manufacturing technology, semiconductor devices are developing towards higher component density and higher integration in order to achieve higher computing speed, larger data storage capacity, and more functions. Therefore, , the gates of complementary metal oxide semiconductor (ComplementaryMetalOxideSemiconductor, CMOS) transistors are becoming thinner and shorter than before. In order to obtain better electrical performance, it is usually necessary to improve the performance of semiconductor devices by controlling the carrier mobility. A key element in controlling carrier mobility is controlling the stress in the transistor channel to increase the drive current. [0003] At present, the embedded germanium silicon (EmbeddedGeSi) technology is used to inc...

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L21/336
Inventor 邓浩张彬
Owner SEMICON MFG INT (SHANGHAI) CORP