How to form a pmos transistor
A transistor and gas technology, applied in the field of semiconductor manufacturing, can solve the problems of reducing the performance of PMOS transistors, affecting the stress of the silicon germanium layer, and difficult to control the concentration of germanium, and achieving the effects of increasing the concentration, increasing the stress, and improving the performance.
- Summary
- Abstract
- Description
- Claims
- Application Information
AI Technical Summary
Problems solved by technology
Method used
Image
Examples
Embodiment Construction
[0050] A silicon germanium layer (SiGe) is formed in the source and drain regions of the PMOS transistor, and the compressive stress formed by lattice mismatch between silicon and silicon germanium is introduced to improve the mobility of carriers in the channel region. Usually, the silicon germanium layer The higher the concentration of germanium in the medium, the greater the compressive stress applied by the silicon germanium layer (SiGe), the faster the mobility of carriers in the channel region, and the more the performance of the PMOS transistor is improved. The inventor found in the existing process of making PMOS transistors with silicon-germanium source and drain regions that the existing method of increasing the concentration of germanium in the silicon-germanium layer is to change the flow ratio of germanium source gas and silicon source gas, but this method improves The concentration of germanium in the silicon germanium layer is limited, generally 20% to 30%, and t...
PUM
Login to View More Abstract
Description
Claims
Application Information
Login to View More 