Testing structure, forming method of testing structure and washing time judging method of washing process

Abstract

Provided is a testing structure. The testing structure comprises a substrate, a pattern layer placed on the surface of the substrate, and a detection layer placed on the surface of the pattern layer. The pattern layer at least comprises a first pattern and a second pattern, the area of the first pattern or the area of the second pattern is at least larger than 2500 square microns, and the distance between the first pattern and the second pattern is equal to or smaller than a corresponding design rule. Meanwhile, the invention further provides a forming method of the testing structure and a washing time judging method of washing process by adopting the testing structure. With the methods, proper parameters of manufacturing process can be found, yields of semiconductor devices can be improved, and performance of integrated circuits can be improved.

Description

technical field [0001] The invention relates to the technical field of semiconductor manufacturing, in particular to a test structure and its forming method, and a method for judging the flushing time of the flushing process. Background technique [0002] Current semiconductor fabrication techniques typically employ more than one thin film layer (eg, a multi-layer stack) in order to impart more features to an integrated circuit (IC) chip. Usually, due to the characteristics of the film materials of each layer (such as elasticity, thermal expansion, etc.) and the shape, size and distribution of the graphics on each layer of film are different, stress will be generated inside each layer of film. Moreover, external forces in the manufacturing process (such as temperature rise and fall, impact of high-pressure water column, mechanical pressure and vacuum adsorption, etc.) will also affect the distribution of stress in the films of each layer on the wafer surface. [0003] When ...

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Problems solved by technology

[0003] When the distribution of stress in the thin films on the surface of the wafer is not uniform, or when an inappropriate external force is applied to the thin films on the wafer surface, excessive film stress will be generated locally on the wafer. This excessive film stress It often leads to serious degradation of the properties of thin film materials, such as cracks on the surface of local wafers, which in turn leads to a decrease in the yield of subsequent semiconductor devices and affects the performance of integrated circuits

[0004] The Chinese patent with the publication number "CN1229913A" discloses a "method and device for measuring internal film s

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