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Thin film transistor and its preparation method, array substrate, display device

A thin-film transistor and semiconductor technology, applied in transistors, semiconductor/solid-state device manufacturing, semiconductor devices, etc., can solve the problems of unstable performance and low on-state current, and achieve stable performance, large on-state current, and high display quality. Effect

Active Publication Date: 2018-12-25
BOE TECH GRP CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0005] The technical problems to be solved by the present invention include, aiming at the problems of low on-state current and unstable performance of existing thin-film transistors, to provide a thin-film transistor with high on-state current and stable performance

Method used

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  • Thin film transistor and its preparation method, array substrate, display device
  • Thin film transistor and its preparation method, array substrate, display device
  • Thin film transistor and its preparation method, array substrate, display device

Examples

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Embodiment 1

[0039] This embodiment provides a thin film transistor, which includes a source, a drain, a semiconductor layer, a gate, and a gate insulating layer, and the thin film transistor further includes:

[0040] Provided on the surface of the semiconductor layer, the source conductive layer and the drain conductive layer are spaced apart from each other, the source conductive layer is connected to the source, and the drain conductive layer is connected to the drain; and the source conductive The shortest distance between the layer and the drain conductive layer is smaller than the shortest distance between the source and the drain.

[0041] The thin film transistor of this embodiment is provided with a source conductive layer and a drain conductive layer, and the current on the source and drain can be conducted to the source conductive layer and the drain conductive layer respectively, so the semiconductor used for conduction The length of the region is determined by the shortest di...

Embodiment 2

[0043] This embodiment provides a thin film transistor, such as Figure 2 to Figure 7 As shown, it includes source 3, drain 4, semiconductor layer 1, gate 2, gate insulating layer 21, source conductive layer 31, drain conductive layer 41; wherein, source conductive layer 31 and drain conductive Layer 41 is arranged on the surface of semiconductor layer 1 (that is, both conductive layers 31, 41 are in contact with the surface of semiconductor layer 1), and the two conductive layers 31, 41 are separated from each other (that is, there is no contact between the two conductive layers 31, 41) . And the shortest distance d between the source conductive layer 31 and the drain conductive layer 32 is smaller than the shortest distance between the source 3 and the drain 2 .

[0044] Wherein, as a conventional structure of a thin film transistor, the gate insulating layer 21 should separate the gate 2 from the semiconductor layer 1, and the source 3 and the drain 4 are respectively connec...

Embodiment 3

[0076] This embodiment provides an array substrate, which includes the above thin film transistor.

[0077] Preferably, the array substrate may include a substrate and gate lines and data lines formed on the substrate, the gate lines and the data lines intersect each other and define a plurality of pixel units, each pixel unit is provided with at least one thin film transistor, and At least one of the thin film transistors is the above thin film transistor.

[0078] Of course, other known structures such as storage capacitors, pixel electrodes, organic light emitting diodes, and pixel definition layers (PDLs) should also be provided in the array substrate, which will not be described in detail here.

[0079] Since the array substrate of this embodiment has the above-mentioned thin film transistors, its performance is stable and can be used to realize high-quality display.

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Abstract

The invention provides a thin film transistor and a preparation method thereof, an array substrate and a display device, belonging to the technical field of thin film transistors, which can solve the problems of low on-state current and unstable performance of the existing thin film transistors. The thin film transistor of the present invention includes a source electrode, a drain electrode, a semiconductor layer, a gate electrode, and a gate insulating layer, and further includes: a source electrode conductive layer and a drain electrode conductive layer, which are arranged on the surface of the semiconductor layer and are spaced apart from each other. The source electrode conductive layer is connected to the source electrode, and the drain electrode conductive layer is connected to the drain electrode; and the shortest distance between the source electrode conductive layer and the drain electrode conductive layer is smaller than the shortest distance between the source electrode and the drain electrode. The method for preparing a thin film transistor of the present invention includes the steps of forming the above-mentioned source conductive layer and drain conductive layer. The array substrate and the display device of the present invention include the above-mentioned thin film transistor. The thin film transistor of the present invention can be used in display devices, especially in liquid crystal display devices and organic light emitting diode display devices.

Description

technical field [0001] The invention belongs to the technical field of thin film transistors, and in particular relates to a thin film transistor, a preparation method thereof, an array substrate, and a display device. Background technique [0002] Thin Film Transistor (Thin Film Transistor) is a thin film semiconductor device, which is widely used in display technology (liquid crystal display technology, organic light emitting diode display technology), integrated circuit technology and other fields. [0003] The structure of a top-gate thin film transistor is as follows figure 1 As shown, the semiconductor layer 1 (active layer) is arranged on the substrate 9, the gate insulating layer 21 and the gate 2 are arranged in sequence above the middle of the semiconductor layer 1, and the semiconductor layer 1 (including the gate 2 and the gate insulating layer 21) The whole is covered by the protective layer 5, and the semiconductor layer 1 on both sides of the gate insulating ...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L29/786H01L21/336
CPCH01L29/41733H01L29/45H01L29/458H01L29/78618H01L29/66969H01L29/7869H01L21/47635
Inventor 陈海晶王东方姜春生
Owner BOE TECH GRP CO LTD