Testing shell suitable for on-chip network embedded type IP core

Abstract

The invention discloses a testing shell suitable for an on-chip network embedded type IP core and belongs to the technical field of embedded type IP core testing. The testing shell suitable for the on-chip network embedded type IP core comprises a parallel input port, a parallel bypass temporary storage, a parallel output port, a serial input port, a serial bypass temporary storage, a serial output port, a testing control temporary storage, a first multiplexer, a parallel testing response comparator, a serial testing response comparator, a correct testing response signal parallel input port and a correct testing response signal serial input port. Testing stimulus and correct testing response are simultaneously sent in an IP core to be tested, only one data sub-package is needed to complete testing, and the transmitting data size can be effectively reduced for a multicast transmission mode.

Description

technical field [0001] The invention discloses a test shell suitable for an embedded IP core of an on-chip network, and belongs to the technical field of embedded IP core testing. Background technique [0002] The design of NoC (Network-on-Chip, network on chip) adopts the same design pattern based on IP core multiplexing as SoC (System on Chip, system on chip). Improve the design efficiency of NoC and shorten the development cycle. The multiplexing of IP core includes not only the multiplexing of circuit logic, but also the testing multiplexing of IP core. When a large number of IP cores are embedded in the NoC, the external pins of the chip can only access the ports of the IP cores through the data packet forwarding mode. The original test method of a single IP core is no longer applicable to the integrated IP core, thus The embedded IP core test port loses its original observability and controllability. In addition, the multiplexed IP cores come from different companie...

AI Technical Summary

Problems solved by technology

[0005] The existing test interface design scheme is only suitable for the test of the embedded IP core in the common unicast mode. The disadvantage is that it does not mention the test optimization effect of the specific NoC under the specific structure, and it is less adaptable to other test modes. Poor, i.e. not suitable for multicast test mode

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