System and method for signature-based redundancy comparison

Abstract

A system and method for signature-based redundancy comparison provides for receiving, by a master part, an input signal and generating, by the master part, a binary output signal, generating a delayed input signal based on the input signal, generating a first output signature based on the binary output signal, and generating a delayed first output signature based on the first output signature. The system and method further comprise generating a delayed binary output signal based on the delayed input signal, generating, by a checker part, a delayed second output signature based on the delayed binary output signal, comparing the delayed first output signature with the delayed second output signature, and generating an error signal, where the state of the error signal is based upon the comparison.

Description

[0001] Cross References to Related Applications [0002] This application is related to the US Patent Application Serial No. __, entitled "Apparatus and Method for Comparing Binary Character Pairs", filed concurrently with it on __, the contents of which are hereby incorporated by reference. technical field [0003] Certain embodiments of the invention relate to providing diagnostic coverage in computing systems and methods. More specifically, certain embodiments of the present invention relate to systems and methods for generating diagnostic signatures within redundant systems for fault detection, including common cause faults, logical stuck-at faults ( stuck-at-faults) and cross-coupling faults. Background technique [0004] Functional integration within an electronic control unit (ECU) is mainly concentrated around the safety microcontroller, which plays a central role by hosting critical computing and control functions. As a result of submicron technology, it is possib...

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Problems solved by technology

[0005] However, typical duplex systems require cycle-by-cycle hardware-based comparisons of each function's output, as well as complex, common-cause failure analysis based on delaying redundant components by one or more clock cycles, e.g. Large power consumption and large chip area associated with duplex structure integration

[0006] Also, the large duplex system results in input and output latency costs, and complex comparator logic

For example, for a delay of 2 cycles, assuming 1000 inputs and 1000 outputs, the delay cost is 4000 flip-flops

In addition to the area required to integrate a large number of flip-flops, power consumption becomes a limiting factor when scaling such systems and when operating at higher frequencies that typically require higher latencies (i.e., larger numbers of delay cycles)

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