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Shift register and drive method thereof

A technology of shift register and driving method, which is applied in the direction of static memory, digital memory information, instruments, etc., can solve the problem of distortion of the output signal of the shift register, and achieve the effect of preventing distortion and improving reliability

Active Publication Date: 2013-09-11
SHANGHAI TIANMA MICRO ELECTRONICS CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0008] The purpose of the present invention is to provide a shift register and its driving method to solve the problem of serious distortion of the output signal of the shift register in the prior art

Method used

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  • Shift register and drive method thereof

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Experimental program
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Embodiment 1

[0037] Please refer to image 3 , which is a schematic structural diagram of a shift register according to an embodiment of the present invention. Such as image 3 As shown, the shift register includes: a first transistor M1, a second transistor M2, a third transistor M3, a fourth transistor M4, and a fifth transistor M5, wherein,

[0038]The gate of the first transistor M1 is connected to the output terminal OUT of the shift register, its drain is connected to the first level signal terminal VGH1, its source is connected to the drain of the second transistor M2 and the fourth transistor M4 the gate connection;

[0039] The gate of the second transistor M2 is connected to the first clock signal terminal CK, and its source is connected to the second level signal terminal VGL1;

[0040] The gate of the third transistor M3 is connected to the first clock signal terminal CK, its source is connected to the input terminal IN of the shift register, and its drain is connected to th...

Embodiment 2

[0058] The difference between the second embodiment and the first embodiment is that for image 3 In the shift register shown, the transistors (the first transistor M1 , the second transistor M2 , the third transistor M3 , the fourth transistor M4 and the fifth transistor M5 ) are NMOS transistors.

[0059] Among them, the working timing of the shift register please refer to Figure 5 , the input signal of the first level signal terminal VGL2 is a low level signal, the input signal of the second level signal terminal VGH2 is a high level signal, the input terminal IN of the shift register is connected to a high level pulse signal, the first The clock signal terminal CK is connected to the first clock signal ck, and the second clock signal terminal CKB is connected to the second clock signal ckb, wherein the second clock signal ckb is an inverted signal of the first clock signal ck.

[0060] Please continue to refer Figure 5 , specifically, the shift register mainly includes...

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Abstract

The invention provides a shift register and a drive method thereof. The shift register comprises first to fifth transistors, wherein the grid electrode of the first transistor is connected with an output end; the drain electrode of the first transistor is connected with a first level signal end; the source electrode of the first transistor is connected with the drain electrode of the second transistor and the grid electrode of the fourth transistor; the grid electrode of the second transistor is connected with a first clock signal end; the source electrode of the second transistor is connected with a second level signal end; the grid electrode of the third transistor is connected with the first clock signal end; the source electrode of the third transistor is connected with an input end; the drain electrode of the third transistor is connected with the grid electrode of the fifth transistor; the drain electrode of the fourth transistor is connected with the first level signal end; the source electrode of the fourth transistor is connected with the output end; a first capacitor is connected with the grid electrode and the drain electrode of the fourth transistor; the source electrode of the fifth transistor is connected with a second clock signal end; the drain electrode of the fifth transistor is connected with the output end; a second capacitor is connected with the grid electrode and the drain electrode of the fifth transistor. When the output end needs to be kept, stable first level signals are always obtained from the first level signal end, so that the problem of distortion of output signals is prevented.

Description

technical field [0001] The invention relates to a gate driving device, in particular to a shift register in a liquid crystal display driving circuit and a driving method thereof. Background technique [0002] In today's era of rapid technological development, liquid crystal displays have been widely used in electronic display products, such as televisions, computers, mobile phones and personal digital assistants. The liquid crystal display includes a source driver (Source Driver), a gate driver (Gate Driver) and a liquid crystal display panel. The liquid crystal display panel has a pixel array, and the gate driver is used to sequentially turn on corresponding pixel rows in the pixel array, so as to transmit the pixel data output by the data driver to the pixels, and then display the image to be displayed. [0003] Current technologies mostly use shift registers (Shift Registers) to implement gate drivers that can sequentially turn on corresponding pixel rows in the pixel ar...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G11C19/28G09G3/36
CPCG11C19/28G11C19/184G09G3/3674G09G2310/0286G09G3/3677G09G3/3611H03K17/161
Inventor 钱栋曾章和
Owner SHANGHAI TIANMA MICRO ELECTRONICS CO LTD
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