A self-aligned graphene field effect transistor and its preparation method

Abstract

The invention discloses a self-aligned graphene field effect transistor and a manufacturing method thereof. The self-aligned graphene field effect transistor comprises a semiconductor substrate, an insulating layer, a conducting channel, a source electrode, a drain electrode, a gate dielectric layer, gate metal, self-aligned metal, the insulating layer is formed on the semiconductor substrate, the conducting channel is is formed on an insulator and formed by graphene, the source electrode and the drain electrode are formed on two sides of the conducting channel respectively, the gate dielectric layer selectively deposits on the conducting channel between the source electrode and the drain electrode, the gate metal is formed on the gate dielectric layer, and the gate dielectric layer and the gate metal are simultaneously and graphically piled together to form a gate accumulation layer to control carrier concentration of a channel area. A self-aligned metal layer covers on the source electrode, the drain electrode, the conducting channel and the gate metal, so that the area of a region not being covered by a grid and self-aligning of a device grid and the source electrode as well as the drain electrode is realized.

Description

technical field [0001] The invention belongs to the technical field of field-effect transistor manufacturing, and in particular relates to a self-aligned graphene field-effect transistor and a preparation method thereof. Background technique [0002] Nanoelectronics based on carbon materials, especially graphene (Graphene) material, due to its high carrier mobility and saturation velocity, and its two-dimensional planar structure can be integrated with the traditional Si process, it is considered to have It has great application prospects and is considered to be a new material for the next generation of integrated circuits that can replace silicon. Since graphene was successfully developed in 2004, research on graphene devices has made great progress. Graphene-based micro-nano electronic devices have the characteristics of small size, fast speed, low power consumption, and simple process, and have attracted more and more attention. [0003] Graphene field-effect transistor...

AI Technical Summary

Problems solved by technology

[0004] In a graphene field effect transistor, in order to reduce the parasitic capacitance between the gate and the source-drain electrodes, a certain passage area needs to be reserved between the gate-source and the gate-drain. Since graphene has a single atomic layer structure, its own square resistance very big

In addition, since the graphene in the access region is not regulated by the gate voltage, the Fermi level is close to the Dirac point, and the electron energy state density is low, which will also produce a large resistance.

In traditional silicon-based field-effect transistors, the resistance of the access region can be reduced by doping, but this is not applicable in graphene field-effect transistors, because graphene is a two-dimensional structure, and direct doping will destroy graphene. Full lattice adversely affects device characteristics

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