CMOS device and manufacturing method thereof

Abstract

The invention discloses a CMOS device which comprises a first MOSFET, a second MOSFET, a first stress layer and a second stress layer. The second MOSFET is different from the first MOSFET in type. The first stress layer covers the first MOSFET and has first stress. The second stress layer covers the second MOSFET, and is provided with doping ions so as to have second stress which is different from the first stress. According to the CMOS device and a manufacturing method thereof, the method of partition ion injection is used for achieving a double-stress pad layer, photoetching / etching is needless for removing a tensile stress layer on a PMOS area or a pressure stress layer on an NMOS area, the technology is simplified, cost is lowered, and meanwhile the probable damage of the heat process of a sedimentation technology on the stress of the pad layer of the NMOS area or the stress of the pad layer of the PMOS area is also avoided.

Description

technical field [0001] The invention relates to a CMOS device and a manufacturing method thereof, in particular to a CMOS device and a manufacturing method thereof which change the properties of a stress layer through doping. Background technique [0002] Various stress engineering techniques have been widely used in sub-130nm technology and below technology generations. A central consideration for using stress engineering in CMOS technology is that PMOS and NMOS respond differently to different types of stress. Specifically, PMOS performance is improved by applying compressive stress to the channel region, while NMOS performance is improved by applying tensile stress to the channel region. [0003] One major approach involves the use of stress-inducing overlays. CVD silicon nitride is a common choice for the stress cap layer, and the magnitude and type of stress can be changed by adjusting deposition conditions such as temperature and frequency. Standard photolithography...

AI Technical Summary

Problems solved by technology

This method effectively avoids the problems caused by changes in the stress size and type of the SiN capping layer caused by changes in process parameters, but for PMOS and NMOS devices, different substrates, such as SiGe and SiC, are required, which makes CMOS not fully compatible with The existing single Si substrate process requires additional growth of SiGe or SiC on the Si substrate, the process is more complicated, and it is difficult to adjust various parameters

[0005] In short, in the existing stress MOSFET, the traditional stress provision method is complicated in process, high in cost and low in reliability. Therefore, there is an urgent need for a new type of stress that can effectively control the channel stress, increase the carrier mobility, and improve the performance of the device. CMOS device and its manufacturing method

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