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Method for protecting shallow trench isolation regions

A technology of shallow trench isolation region and shallow trench is applied in the field of protection of shallow trench isolation region, which can solve the problems of non-disclosure and the like, and achieve the effects of increasing yield, less modification of process steps, and improved device performance.

Active Publication Date: 2015-11-25
SHANGHAI HUALI MICROELECTRONICS CORP
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  • Abstract
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Problems solved by technology

This patent document also does not disclose the technical characteristics of how to reduce the damage to the STI in the wet process of the low-voltage device during the preparation of the high-voltage integrated circuit, thereby avoiding the formation of dents and the leakage of the device

Method used

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  • Method for protecting shallow trench isolation regions
  • Method for protecting shallow trench isolation regions
  • Method for protecting shallow trench isolation regions

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Embodiment Construction

[0029] The specific embodiment of the present invention will be further described below in conjunction with accompanying drawing:

[0030] Figure 2-9 It is a schematic structural flow diagram of an embodiment of the method for protecting shallow trench isolation regions of the present invention; as Figure 2-9 As shown, a method for protecting shallow trench isolation regions is applied in the preparation process of high-voltage devices compatible with low-voltage devices, and specifically includes the following steps:

[0031] Firstly, a substrate 3 having a high-voltage device region 2 and a low-voltage device region 1 is provided, and a thickness of (preferably or etc.) the oxide layer 4 and a thickness of (preferably or etc.) sacrificial nitride layer 5; wherein, the oxide layer 4 covers the upper surface of the substrate 3, and the sacrificial nitride layer 5 covers the upper surface of the oxide layer 4, and then forms such as figure 2 structure shown....

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Abstract

The invention relates to the field of high-voltage integrated circuits, in particular to a method for protecting a shallow trench isolation region. The method for protecting the shallow trench isolation region, provided by the invention, is applied to the process of high-voltage integrated circuits, when high-voltage devices and low-voltage devices are prepared, by preparing nitride as an STI protective layer on the low-voltage device region before growth of the gate oxide for the high-voltage devices, sink defects of STI in follow-up wet processing can be avoided, further the product yield is increased; the process steps are altered less; and the method has the advantage of high compatibility with the conventional technological process, and improvement on the device performance can be achieved easily.

Description

technical field [0001] The invention relates to the field of high-voltage integrated circuits, in particular to a method for protecting shallow trench isolation regions. Background technique [0002] With the reduction of critical dimensions in IC manufacturing, the wafer must be clean before entering the process, which requires repeated cleaning steps to remove pollutants on the wafer surface such as particles, organic matter, metal and natural oxidation. Layers, etc., and the number of cleanings depends on the complexity of the wafer design and the number of interconnected layers. The semiconductor IC industry mainly adopts wet cleaning process for wafer cleaning, such as tank cleaning, spin washing and drying, single chip corrosion cleaning, etc. [0003] At present, in the process of high-voltage integrated circuits, in order to be compatible with low-voltage devices and medium-voltage devices, its process flow is more complicated than that of medium-voltage or low-volt...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L21/762
Inventor 沈萍马旭曹亚民
Owner SHANGHAI HUALI MICROELECTRONICS CORP
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