169 results about "High voltage integrated circuits" patented technology

Design structures for high-voltage integrated circuits. The design structure, which is formed using a semiconductor-on-insulator (SOI) substrate, may include device structure with a semiconductor body positioned between first and second gate electrodes. The first and second gate electrodes and the semiconductor body may be formed from the monocrystalline SOI layer of the SOI substrate. A dielectric layer separates each of the first and second gate electrodes from the semiconductor body. These dielectric layers are formed by defining trenches in the SOI layer and filling the trenches with a dielectric material, which may occur concurrently with a process forming other device isolation regions.

A high voltage circuit driver includes high and low side driver cells to drive a high and a low side power MOSFET, a bootstrap circuit to energize the high side driver cell, a high voltage PMOS transistor (HVPMOS) between a voltage source and the bootstrap circuit, wherein the HVPMOS is embedded in an N-isolation layer and is integrated with the driver cells. A bootstrap control circuit, for controlling the HVPMOS, includes a high voltage level shift stage, which can also be embedded in an N-isolation layer. The circuit driver is operated by switching the high side drive signal from high to low, the low side drive signal from low to high with a first delay, and a bootstrap control signal from high to low with an additional second delay. Also, the bootstrap capacitor is first charged by switching on the HVPMOS, and then it energizes the high side driver cell.

A circuit including at least one low voltage input, at least one high voltage output, and a field transistor having a source, a drain and a control region. The circuit may comprise a high-voltage amplifier. In this embodiment, an electrical connection between the high-voltage output terminal and the field transistor control region, and an electrical connection between the input terminal and a second transistor. Various embodiments of the field transistor are described.

An HNMOS transistor (4) has its drain electrode connected to the gate electrode of an NMOS transistor (21), and a logic circuit voltage (VCC) is applied to the drain electrode of the NMOS transistor (21) through a resistor (32). A ground potential is applied to the source electrode of the NMOS transistor (21). A drain potential (V2) at the NMOS transistor (21) is monitored by an interface circuit (1), for indirectly monitoring a potential (VS). Thus provided is a high voltage integrated circuit for preventing damage to a semiconductor device used for performing bridge rectification of a power line.

The present invention includes processes and packaging for high voltage integrated circuits (ICs), high voltage electronic devices and high voltage electronic circuits which operate over a wide range of voltages, e.g., from tens of volts to tens of thousands of volts. The inventive processes and packaging are particularly suitable for integrating low or lower voltage circuits or transistors to form high voltage ICs, high voltage electronic devices and high voltage electronic circuits. The inventive processes and packaging are also particularly suitable for isolating high voltage electronics to achieve high breakdown voltages and for supporting high voltage operation. The inventive processes may be used with any suitable semiconductor materials using conventional semiconductor fabrication and related facilities.

A high voltage integrated circuit contains a freewheeling diode embedded in a transistor. It further includes a control block controlling a high voltage transistor and a power block—including the high voltage transistor—isolated from the control block by a device isolation region. The high voltage transistor includes a semiconductor substrate of a first conductivity type, a epitaxial layer of a second conductivity type on the semiconductor substrate, a buried layer of the second conductivity type between the semiconductor substrate and the epitaxial layer, a collector region of the second conductivity type on the buried layer, a base region of the first conductivity type on the epitaxial layer, and an emitter region of the second conductivity type formed in the base region. The power block further includes a deep impurity region of the first conductivity type near the collector region to form a PN junction.

A clamp circuit includes both nmos and pmos devices connected in series between a voltage source terminal, such as an integrated circuit pad, and ground. A trigger unit, connected between the voltage source and ground, includes a plurality of output terminals coupled to the clamp circuit. The trigger unit is responsive to a voltage threshold, such as caused by an ESD occurrence, between the voltage source and ground to apply clamping signals at its output terminals to couple the voltage source terminal to ground through both nmos and pmos devices.

The invention relates to a semiconductor device used for an SOI (silicon-on-insulator) high-voltage integrated circuit, belonging to the field of power semiconductor devices. The semiconductor device comprises a semiconductor substrate layer, a dielectric buried layer and a silicon top layer, wherein at least high-voltage LIGBT (lateral insulated gate bipolar transistor), NLDMOS (N-type lateral double-diffused metal-oxide semiconductor) and PLDMOS (P-type lateral double-diffused metal-oxide semiconductor) devices are integrated in the silicon top layer; the thickness of the dielectric buried layer is not more than 5 mum; the thickness of the silicon top layer is not more than 20 mum; multiple incontinuous high-concentration N<+> regions (doping concentration is not lower than 1e16e cm<-3>) are formed at the bottoms of the high-voltage devices and the silicon top layer above the surface of the dielectric buried layer; the high-voltage devices are isolated by dielectric isolation regions; low-voltage MOS (metal oxide semiconductor) devices can also be integrated in the device; the high-voltage devices and low-voltage devices are isolated by the dielectric isolation regions; and different low-voltage devices are isolated by field oxidation layers. The semiconductor device has the advantages that: because of the introduction of the multiple incontinuous high-concentration N<+> regions, the electric field of the silicon top layer is weakened and the electric field of the dielectric buried layer is enhanced at the same time, the breakdown voltage of the device is greatly improved, and the device can be applied in high-voltage integrated circuits in the automobile electronics, consumption electronics, green lighting, industrial control, power supply management, display driving and other fields.

A high voltage PMOS device having an improved breakdown voltage is achieved. An asymmetrical high voltage integrated circuit structure comprises a gate electrode on a substrate and source and drain regions within the substrate on either side and adjacent to the gate electrode wherein the source region is encompassed by an n-well. A symmetrical high voltage integrated circuit structure comprises a gate electrode on a substrate, source and drain regions within the substrate on either side and adjacent to the gate electrode, and an n-well in the substrate underlying the gate electrode. The n-well in both structures shifts the breakdown point from the silicon surface to the bottom of the source or drain regions.

A high-voltage integrated circuit device has formed therein a high-voltage junction terminating region that is configured by a breakdown voltage region formed of an n-well region, a ground potential region formed of a p-region, a first contact region and a second contact region. An opposition section of the high-voltage junction terminating region, whose distance to an intermediate-potential region formed of a p-drain region is shorter than those of other sections, is provided with a resistance higher than those of the other sections. Accordingly, a cathode resistance of a parasitic diode formed of the p-region and the n-well region increases, locally reducing the amount of electron holes injected at the time of the input of a negative-voltage surge. As a result, an erroneous operation or destruction of a logic part of a high-side circuit can be prevented when the negative-voltage surge is applied to an H-VDD terminal or a Vs terminal.

A circuit including at least one low voltage input, at least one high voltage output, and a field transistor having a source, a drain and a control region. The circuit may comprise a high-voltage amplifier. In this embodiment, an electrical connection between the high-voltage output terminal and the field transistor control region, and an electrical connection between the input terminal and a second transistor. Various embodiments of the field transistor are described.

Provided is a high-voltage integrated circuit device including a high-voltage resistant diode. The device includes a low-voltage circuit region having a plurality of semiconductor devices, which operate with respect to a ground voltage, a high-voltage circuit region having a plurality of semiconductor devices, which operate with respect to a voltage that varies from the ground voltage to a high voltage, a junction termination and a first isolation region electrically isolating the low-voltage circuit region from the high-voltage circuit region, a high-voltage resistant diode formed between the low-voltage circuit region and the high-voltage circuit region, and a second isolation region surrounding the high-voltage resistant diode and electrically isolating the high-voltage resistant diode from the low-voltage circuit region and the high-voltage circuit region. Therefore, a leakage current of the high-voltage resistant diode can be prevented.

The invention discloses a circuit with an electrostatic protection function, a high-voltage integration circuit and an air conditioner. The circuit with the electrostatic protection function comprisesa voltage detection circuit, a main discharge circuit and a circuit to be protected. The voltage detection circuit is used for detecting an electrostatic voltage between a power supply line and a grounding line. The main discharge circuit is arranged to provide a main discharge channel for a static current. The circuit to be protected comprises a main circuit unit to be protected and an auxiliaryprotection circuit. The auxiliary protection circuit can carry out secondary discharge on electrostatic energy which is not completely discharged from the main discharge circuit, and simultaneously can discharge the electrostatic energy entered from the signal input end of the main circuit unit to be protected so as to prevent static electricity from entering into the main circuit unit to be protected via ports except for the power supply line and the grounding line. In the technical scheme, electrostatic protection is performed on the main circuit unit to be protected simultaneously from thepower supply line and a signal line and the electrostatic protection capability of an integral circuit is increased.

The invention provides an integrated power device on a silicon on insulator (SOI) layer for negative supply voltage, belonging to the field of semiconductor power devices. The integrated power device on the SOI layer for the negative supply voltage is characterized in that the SOI layer is integrated with at least two or three high-voltage devices of an n-type lateral insulated gate bipolar transistor (nLIGBT), a p-type laterally diffused metal oxide semiconductor (pLDMOS) and an n-type laterally diffused metal oxide semiconductor (nLDMOS), and also can be integrated with a low-voltage metal oxide semiconductor (MOS) device; buried oxide layers and dielectrically isolated areas connected with the buried oxide layer are used to realize the complete isolation among the different devices; a conventional local oxidation of silicon (LOCOS) technology or a shallow trench isolation technology is adopted for realizing the dielectrically isolated area; the SOI layer is 0.5-3mu m in thickness; and the dielectric electric-field strength of the thick gate oxide layer of the high-voltage nLIGBT and nLDMOS devices is less than 5*106V / cm so as to meet the requirements of the high-voltage integrated circuit of the negative supply voltage for high voltage resistance between the grid electrodes and source electrodes of the devices. The integrated power device on a SOI layer for the negative supply voltage has the advantages of small parasitic effect, fast speed, low power consumption, strong irradiation resistance and the like, realizes compatibility of the high-voltage devices with the low-voltage devices, and meets the requirements of the working environment of the negative supply voltage. The integrated power device on a SOI layer for the negative supply voltage is used to manufacture a plurality of high-voltage, high-speed and low conducting-loss power devices with good performances, and is used for the high-voltage application of the negative supply voltage.

The invention describes a programming charge pump circuit of obtaining the different voltage and especially simultaneously produces the positive and negative voltages; its circuit diagram saw the abstract attached figure. This invention through the minority electric capacity sigal output node to achieve the different output voltage goal, simultaneously separately may altogether use the electric capacity when produces positive and negative voltage. This invention electric charge pumps may use in the highpressure integrated circuit chip, it has realized the low power loss, high efficiency, And may act according to the actual request to expand this circuit structure to the need voltage. This invention electric charge pumps has the modular construction and agility remove match function and can achieve the programmable output voltage value through the control logic control clock succession. This electric charge pumps effectiveness lie in its structure used less electric capacities, and reasonable used level transfer circuit produce the high voltage through less progressions. This electric charge pump's low power loss lie in designs used the non- overlap succession to greatest degree reduce direct current to arrive the place path.

A high-voltage integrated circuit device can include, in a surface layer of a p semiconductor substrate, an n region which is a high-side floating-potential region, an n− region which becomes a high-voltage junction terminating region, and an n− region which is an L-VDD potential region. A low-side circuit portion can be disposed in an n− region. Below a pickup electrode disposed in the high-voltage junction terminating region, a universal contact region in Ohmic contact with the pickup electrode can be disposed. The universal contact region has a p+ region and an n+ region that can be disposed in alternating contact along a surface of the p semiconductor substrate. By disposing the universal contact region in this way, the quantity of carriers flowing into the low-side circuit portion can be reduced when a negative surge voltage is input. Consequently, erroneous operation due to latchup of a logic portion can be minimized.

The invention relates to a time-delay circuit for a high-voltage integrated circuit. The time-delay circuit for the high-voltage integrated circuit consists of a limit narrow time-delay circuit, a pulse generation circuit and a level conversion circuit. An input signal is connected to the input end of the limit narrow time-delay circuit; the output end of the limit narrow time-delay circuit is connected with the input end of the pulse generation circuit; both output ends of the pulse generation circuit are connected with both input ends of the level conversion circuit; and the limit narrow time-delay circuit is used for realizing the function of the conventional time-delay circuit when the pulse width of the input signal VIN is wider, generating a time delay TON for the rising edge of theinput signal VIN and generating a time delay TOFF for the falling edge of the input signal VIN, making TON greater than TOFF, and ensuring that the pulse width of the signal passing through the limitnarrow time-delay circuit is more than or equal to a predetermined value TMIN when the pulse width f the input signal VIN is narrower. The circuit can guarantee that all input signals in a low-voltage region can be transmitted successfully to a high-voltage region, and avoids error operation of the high-voltage integrated circuit so as to effectively enhance the reliability of the high-voltage integrated circuit.

The invention provides a VS transient negative voltage endurance capacity testing device for a high-voltage integrated circuit. The VS transient negative voltage endurance capacity testing device comprises a half-bridge drive circuit and a negative voltage generating circuit, wherein the negative voltage generating circuit comprises a control circuit, a first switching device and a negative voltage adjusting power supply; the control circuit can be connected with an HIN signal input end of the high-voltage integrated circuit and used for generating a pulse signal with a preset pulse width and driving the first switching device to be switched on and off; the output end of the first switching device is connected to an output node of the half-bridge drive circuit, and the input end of the first switching device is connected to the negative voltage adjusting power supply; and when the first switching device is electrified, the negative voltage which is equal to the absolute value of the negative voltage adjusting power supply is overlaid onto the output node of the half-bridge drive circuit. The invention also provides a testing method. According to the testing device provided by the invention, the negative voltage generating circuit is additionally arranged on the basis of the half-bridge driving circuit and can generate the VS transient negative voltage of which the amplitude and the duration time can be continuously adjusted, and therefore the VS transient negative voltage endurance capacity of the high-voltage integrated circuit can be tested.

The invention discloses a high-integrated intelligent power module, wherein a logic control circuit and a drive circuit are arranged in the high-integrated intelligent power module IPM3, the high-integrated intelligent power module IPM3 generates two paths of output, the first path of output is U3, V3 and W3, the second path of output is U4, V4 and W4, wherein the first path of output drives an inverter compressor M3 of an inverter air conditioner, and the second path of output drives an inverter fan M4 of the inverter air conditioner. The high-integrated intelligent power module IPM3 comprises a control chip MCU2, a high-voltage integrated circuit HVIC3, a first analog switch K1, a second analog switch K2 and a third analog switch K3, wherein the control chip MCU2 controls the high-voltage integrated circuit HVIC3 through a first control signal PRO3, and controls the first analog switch K1 through a second control signal PRO4. The high-integrated intelligent power module has the characteristics of simple and reasonable structure, flexibility for operation, low manufacturing cost, high reliability and wide application scope.

Through different voltage controller, the charge pump circuit selects required output voltage. Different switching capacitors are utilized to reach voltage needed for programmable LCD driving circuit. In the invention, different output voltages are outputted from single output node through few capacitors. Being applicable to IC chip in high voltage, the charge pump realizes low power waste and high efficiency. The structure of the circuit can be extended in order to obtain voltage needed based on requirement. Features are: modular construction, programmable value of output voltage reached through logic controlled clock time sequence, high voltage generated from few stages of level carry circuit and few capacitors.

A high voltage integrated circuit device suppresses the quantity of holes that are implanted due to a negative voltage surge, thus preventing malfunction and destruction of a high side circuit. A p−-type aperture portion has a gap portion in an n-type well region that is a voltage resistant region, penetrating the n-type well region to reach a p-type substrate, so as to enclose an n-type well region that is a high potential region.

The invention provides an under-voltage protection circuit for solving the problems that an under-voltage protection circuit is multiple in used component, slow in response and the like in the prior art. The under-voltage protection circuit comprises a potential-divider network, a pull-up circuit, an under-voltage protection signal output control switch and an under-voltage protection signal output end. The potential-divider network is used for conducting voltage dividing on a driving source to output second voltage signals so that the under-voltage protection signal output control switch can be controlled to be switched off and switched on. The pull-up circuit is connected between the driving source and the under-voltage protection signal output control switch, and the under-voltage protection signal output end is connected between the pull-up circuit and the under-voltage protection signal output control switch. When the under-voltage protection signal output control switch is switched off, the pull-up circuit pulls up under-voltage protection signals to be the driving source. When the under-voltage protection signal output control switch is switched on, the pull-up circuit pulls down the under-voltage protection signals to be low level signals. The used components of the under-voltage protection circuit are few. The invention further provides a high-voltage integrated circuit.

A hybrid integrated circuit package for a microbeamformer in an ultrasound probe includes a substrate, a driver circuit for generating transmit pulses to be transmitted to the transducer elements of the probe for producing a transmit beam, and a beamformer circuit including time delay circuits and a summation circuit, the time delay circuits being operatively arranged for receiving a plurality of reflected pulses from the transducer elements and delaying the reflected pulses and the summation circuit operatively arranged summing groups of the delayed reflected pulses for producing beamformed signals. The driver circuit is part of a high voltage integrated circuit device including said driver circuit. At least a portion of the beamformer circuit is part of a low voltage integrated circuit device, wherein the high voltage integrated circuit and the low voltage integrated circuit are mounted on the substrate.

The invention discloses a high-voltage transistor model method with an expandable drift region resistor. The method includes the following steps: step 1, a drain-side drift region is divided into three portions according to a device structure, and the three portions include a drift region Lover1d under a ditch active area, a drift region Ldrift1 under filed oxygen and a drift region Ldrift2 under a drain active area; and a source-side drift region is also divided into three portions: a drift region Lovers under the ditch active area, a drift region Ldrifts1 under the field oxygen and a drift region Ldrifts2 under a source active area; and step 2, a resistor property of drift regions of each portion is simultaneously simulated, and effects of gate source voltage Vgs, drain source voltage Vds and body source voltage Vbs of a device on the drift region resistor property are simulated through the following formula. By means of the high-voltage transistor model method, precision of a high-voltage metal oxide semiconductor (MOS) model or a high-voltage laterally diffused metal oxide semiconductor (LDMOS) model can be effectively improved, simulation precision of a high-voltage integrated circuit is improved, and a circuit design period is shortened.