Multi-core processor on-chip network system based on FPGA and provided with accelerator

Abstract

The invention discloses a multi-core processor on-chip network system based on the FPGA and provided with an accelerator. A processor in a main control unit of processor nodes of the system is connected with a data memorizer BRAM2 through a first AXI bus; the processor is connected with the data memorizer BRAM2 sequentially through a Cache interface of the processor and a second AXI bus, and when the first AXI bus is busy or occupied, the processor reads and processes data in the data memorizer BRAM2 through the second AXI bus. The system improves the utilizing rate of the processor and the utilizing rate of each device, and the system is high in arithmetic speed and good in overall performance.

Description

technical field [0001] The invention belongs to the field of integrated circuit design, and in particular relates to an FPGA-based multi-core processor on-chip network system with an accelerator. Background technique [0002] With the development of information technology, the requirements for the computing power of the processor are getting higher and higher. Traditional single-core processors have been unable to meet the needs, resulting in the emergence of multi-core processors. A multi-core processor refers to the integration of two or more processor cores in one processor. By dividing tasks among the cores, the parallel operation of multiple processor cores is realized, thereby improving the operation and processing of the entire processor. ability. There are fewer global signal lines in the multi-core processor, which can better overcome the signal delay. It also has advantages in design, and can use IP multiplexing technology to shorten the design and verification ...

AI Technical Summary

Problems solved by technology

[0009] The purpose of the present invention is to overcome the low problem of the overall performance of the multi-core processor network system on chip existi

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